On Tue, Jun 10, 2014 at 04:42:50PM +0300, Imre Deak wrote:
> On Wed, 2014-06-04 at 13:45 -0700, Jesse Barnes wrote:
> > This allows the system to enter the lowest power mode during system freeze.
> >
> > v2: delete force wake timer at suspend (Imre)
> > v3: add GT work suspend function (Imre)
> > v4: use uncore forcewake reset (Daniel)
> >
> > Signed-off-by: Kristen Carlson Accardi <kris...@linux.intel.com>
> > Signed-off-by: Jesse Barnes <jbar...@virtuousgeek.org>
> > ---
> > drivers/gpu/drm/i915/i915_drv.c | 4 ++--
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/intel_drv.h | 1 +
> > drivers/gpu/drm/i915/intel_pm.c | 20 ++++++++++++++++++++
> > drivers/gpu/drm/i915/intel_uncore.c | 2 +-
> > 5 files changed, 25 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > b/drivers/gpu/drm/i915/i915_drv.c
> > index 66c6ffb..7148eac 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -521,7 +521,7 @@ static int i915_drm_freeze(struct drm_device *dev)
> > drm_irq_uninstall(dev);
> > dev_priv->enable_hotplug_processing = false;
> >
> > - intel_disable_gt_powersave(dev);
> > + intel_suspend_gt_powersave(dev);
>
> I realized now that we actually do need to enable RC6 explicitly. If we
> get here right after runtime resume, the deferred RC6 enabling might be
> still pending and so RC6 might not be enabled.
Hm, for runtime pm we might schedule the delayed rps work with a 0 delay,
just to get the gpu going faster. Just an aside.
Also some runtime pm vs system suspend tests in igt would be good if we
don't have them yet. And if we have them some analysis why this didn't
blow up in testing (and something to address that gap if feasible).
-Daniel
>
> --Imre
>
> >
> > /*
> > * Disable CRTCs directly since we want to preserve sw state
> > @@ -542,8 +542,8 @@ static int i915_drm_freeze(struct drm_device *dev)
> >
> > i915_save_state(dev);
> >
> > + intel_uncore_forcewake_reset(dev, false);
> > intel_opregion_fini(dev);
> > - intel_uncore_fini(dev);
> >
> > console_lock();
> > intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index bea9ab40..89d6b47 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2084,6 +2084,7 @@ extern void intel_uncore_early_sanitize(struct
> > drm_device *dev);
> > extern void intel_uncore_init(struct drm_device *dev);
> > extern void intel_uncore_check_errors(struct drm_device *dev);
> > extern void intel_uncore_fini(struct drm_device *dev);
> > +extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool
> > restore);
> >
> > void
> > i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index c597b0d..74fbe4d 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -957,6 +957,7 @@ void intel_init_gt_powersave(struct drm_device *dev);
> > void intel_cleanup_gt_powersave(struct drm_device *dev);
> > void intel_enable_gt_powersave(struct drm_device *dev);
> > void intel_disable_gt_powersave(struct drm_device *dev);
> > +void intel_suspend_gt_powersave(struct drm_device *dev);
> > void intel_reset_gt_powersave(struct drm_device *dev);
> > void ironlake_teardown_rc6(struct drm_device *dev);
> > void gen6_update_ring_freq(struct drm_device *dev);
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 1840d15..139eebe 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4864,6 +4864,26 @@ void intel_cleanup_gt_powersave(struct drm_device
> > *dev)
> > valleyview_cleanup_gt_powersave(dev);
> > }
> >
> > +/**
> > + * intel_suspend_gt_powersave - suspend PM work and helper threads
> > + * @dev: drm device
> > + *
> > + * We don't want to disable RC6 or other features here, we just want
> > + * to make sure any work we've queued has finished and won't bother
> > + * us while we're suspended.
> > + */
> > +void intel_suspend_gt_powersave(struct drm_device *dev)
> > +{
> > + struct drm_i915_private *dev_priv = dev->dev_private;
> > +
> > + /* Interrupts should be disabled already to avoid re-arming. */
> > + WARN_ON(dev->irq_enabled);
> > +
> > + flush_delayed_work(&dev_priv->rps.delayed_resume_work);
> > +
> > + cancel_work_sync(&dev_priv->rps.work);
> > +}
> > +
> > void intel_disable_gt_powersave(struct drm_device *dev)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> > b/drivers/gpu/drm/i915/intel_uncore.c
> > index 871c284..741a4e3 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > @@ -316,7 +316,7 @@ static void gen6_force_wake_timer(unsigned long arg)
> > intel_runtime_pm_put(dev_priv);
> > }
> >
> > -static void intel_uncore_forcewake_reset(struct drm_device *dev, bool
> > restore)
> > +void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > unsigned long irqflags;
>
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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