On Fri, Jul 04, 2014 at 11:27:39AM -0300, Paulo Zanoni wrote:
> From: Daniel Vetter <daniel.vet...@ffwll.ch>
>
> Still tacked onto the side, but slowly getting there.
>
> v2: Don't forget the debugfs file.
>
> v3 (from Paulo): Don't forget to check the power domains.
>
> Signed-off-by: Daniel Vetter <daniel.vet...@ffwll.ch>
> Reviewed-by: Damien Lespiau <damien.lesp...@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>
As always, there's nothing replacing testing:
for v3: Reviewed-by: Damien Lespiau <damien.lesp...@intel.com>
--
Damien
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 1 +
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_ddi.c | 19 +++++++++++++++++++
> drivers/gpu/drm/i915/intel_display.c | 9 +++++++++
> 5 files changed, 31 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index e79ddbf..7d72768 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2409,6 +2409,7 @@ static int i915_shared_dplls_info(struct seq_file *m,
> void *unused)
> seq_printf(m, " dpll_md: 0x%08x\n", pll->hw_state.dpll_md);
> seq_printf(m, " fp0: 0x%08x\n", pll->hw_state.fp0);
> seq_printf(m, " fp1: 0x%08x\n", pll->hw_state.fp1);
> + seq_printf(m, " wrpll: 0x%08x\n", pll->hw_state.wrpll);
> }
> drm_modeset_unlock_all(dev);
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 2ec7cb6..c1fa561 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -197,6 +197,7 @@ struct intel_dpll_hw_state {
> uint32_t dpll_md;
> uint32_t fp0;
> uint32_t fp1;
> + uint32_t wrpll;
> };
>
> struct intel_shared_dpll {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3d61a53..654417e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5900,6 +5900,7 @@ enum punit_power_well {
> /* WRPLL */
> #define WRPLL_CTL1 0x46040
> #define WRPLL_CTL2 0x46060
> +#define WRPLL_CTL(pll) (pll == 0 ? WRPLL_CTL1 :
> WRPLL_CTL2)
> #define WRPLL_PLL_ENABLE (1<<31)
> #define WRPLL_PLL_SSC (1<<28)
> #define WRPLL_PLL_NON_SSC (2<<28)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index fae73d3..79cbb5e 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -790,6 +790,8 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
> intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
> intel_crtc->config.shared_dpll = DPLL_ID_WRPLL2;
> }
> +
> + intel_crtc->config.dpll_hw_state.wrpll = val;
> }
>
> return true;
> @@ -1315,6 +1317,21 @@ int intel_ddi_get_cdclk_freq(struct drm_i915_private
> *dev_priv)
> }
> }
>
> +static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
> + struct intel_shared_dpll *pll,
> + struct intel_dpll_hw_state *hw_state)
> +{
> + uint32_t val;
> +
> + if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
> + return false;
> +
> + val = I915_READ(WRPLL_CTL(pll->id));
> + hw_state->wrpll = val;
> +
> + return val & WRPLL_PLL_ENABLE;
> +}
> +
> static char *hsw_ddi_pll_names[] = {
> "WRPLL 1",
> "WRPLL 2",
> @@ -1333,6 +1350,8 @@ void intel_ddi_pll_init(struct drm_device *dev)
> for (i = 0; i < 2; i++) {
> dev_priv->shared_dplls[i].id = i;
> dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
> + dev_priv->shared_dplls[i].get_hw_state =
> + hsw_ddi_pll_get_hw_state;
> }
>
> /* The LCPLL register should be turned on by the BIOS. For now let's
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 1d919ae..594a49f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7587,6 +7587,7 @@ static void haswell_get_ddi_port_state(struct
> intel_crtc *crtc,
> {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_shared_dpll *pll;
> enum port port;
> uint32_t tmp;
>
> @@ -7605,6 +7606,13 @@ static void haswell_get_ddi_port_state(struct
> intel_crtc *crtc,
> break;
> }
>
> + if (pipe_config->shared_dpll >= 0) {
> + pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
> +
> + WARN_ON(!pll->get_hw_state(dev_priv, pll,
> + &pipe_config->dpll_hw_state));
> + }
> +
> /*
> * Haswell has only FDI/PCH transcoder A. It is which is connected to
> * DDI E. So just check whether this pipe is wired to DDI E and whether
> @@ -10436,6 +10444,7 @@ intel_pipe_config_compare(struct drm_device *dev,
> PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
> PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
> PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
> + PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
>
> if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
> PIPE_CONF_CHECK_I(pipe_bpp);
> --
> 2.0.0
>
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