On Mon, Jul 07, 2014 at 11:42:04AM -0700, Rodrigo Vivi wrote:
> With this bit enabled, HW changes the color when compressing frames for
> debug purposes.
>
> ALthough the simple way to enable a single bit is over intel_reg_write,
> this value is overwriten on next update_fbc so depending on the workload
> it is not possible to set this bit with intel-gpu-tools. So this patch
> introduces a persistent way to enable false color over debugfs.
>
> v2: Use DEFINE_SIMPLE_ATTRIBUTE as Daniel suggested
>
> Cc: Daniel Vetter <daniel.vet...@ffwll.ch>
> Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 42
> +++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
> 4 files changed, 51 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index c1b88a8..b049fc5 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1510,6 +1510,47 @@ static int i915_fbc_status(struct seq_file *m, void
> *unused)
> return 0;
> }
>
> +static int i915_fbc_fc_get(void *data, u64 *val)
> +{
> + struct drm_device *dev = data;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> +
> + if (INTEL_INFO(dev)->gen < 5)
> + return -ENODEV;
Did you test this on ILK/SNB? Bspec says the bit is MBZ before IVB.
--
Ville Syrjälä
Intel OTC
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