On Friday, August 08, 2014 7:54 PM, Sonika Jindal wrote: > > From: Sonika Jindal <sonika.jin...@intel.com> > > Rename the defines to have levels instead of values for vswing and > pre-emph levels as the values may differ in other scenarios like low vswing of > eDP1.4 where the values are different. > > Done using following cocci patch for each define: > @@ > @@ > > # define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) > + # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) > > ... > > Signed-off-by: Sonika Jindal <sonika.jin...@intel.com> > --- > drivers/gpu/drm/exynos/exynos_dp_core.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c > b/drivers/gpu/drm/exynos/exynos_dp_core.c > index 4f3c7eb..02602a8 100644 > --- a/drivers/gpu/drm/exynos/exynos_dp_core.c > +++ b/drivers/gpu/drm/exynos/exynos_dp_core.c > @@ -329,8 +329,8 @@ static int exynos_dp_link_start(struct exynos_dp_device > *dp) > return retval; > > for (lane = 0; lane < lane_count; lane++) > - buf[lane] = DP_TRAIN_PRE_EMPHASIS_0 | > - DP_TRAIN_VOLTAGE_SWING_400; > + buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | > + DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
NAK! It makes build error. Please build your patch, before sending the patch. It is a rule when submitting patches. Please, fix it as follows. + buf[lane] = DP_TRAIN_PRE_EMPHASIS_LEVEL_0| + DP_TRAIN_VOLTAGE_SWING_LEVEL_0; Best regards, Jingoo Han > > retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, > lane_count, buf); > -- > 1.7.10.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
