This patch convert necessary GTT read/write calls, e.g. iowrite32() and
readl() et al, to an encapsulated series: GTT_READ32, GTT_WRITE32,
GTT_READ64 and GTT_WRITE64.
This patch doesn't change the behaviors of i915 GTT access.
Signed-off-by: Jike Song <jike.s...@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 23 +++++++++++++++++++++++
drivers/gpu/drm/i915/i915_gem_gtt.c | 33 +++++++++++++++++----------------
2 files changed, 40 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ed6f14e..051442e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3075,6 +3075,29 @@ int vlv_freq_opcode(struct drm_i915_private *dev_priv,
int val);
#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
+#define GTT_READ32(addr) \
+({ \
+ u32 ret = readl(addr); \
+ ret; \
+})
+
+#define GTT_READ64(addr) \
+({ \
+ u64 ret = readq(addr); \
+ ret; \
+})
+
+#define GTT_WRITE32(val, addr) \
+({ \
+ writel((val), (addr)); \
+})
+
+#define GTT_WRITE64(val, addr) \
+({ \
+ writeq((val), (addr)); \
+})
+
+
/* "Broadcast RGB" property */
#define INTEL_BROADCAST_RGB_AUTO 0
#define INTEL_BROADCAST_RGB_FULL 1
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 273dad9..3472970 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -642,7 +642,7 @@ static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt,
struct seq_file *m)
u32 expected;
gen6_gtt_pte_t *pt_vaddr;
dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde];
- pd_entry = readl(pd_addr + pde);
+ pd_entry = GTT_READ32(pd_addr + pde);
expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
if (pd_entry != expected)
@@ -695,9 +695,9 @@ static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
pd_entry |= GEN6_PDE_VALID;
- writel(pd_entry, pd_addr + i);
+ GTT_WRITE32(pd_entry, pd_addr + i);
}
- readl(pd_addr);
+ GTT_READ32(pd_addr);
}
static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
@@ -1365,13 +1365,14 @@ int i915_gem_gtt_prepare_object(struct
drm_i915_gem_object *obj)
return 0;
}
-static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
+static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte,
+ struct drm_i915_private *dev_priv)
{
#ifdef writeq
- writeq(pte, addr);
+ GTT_WRITE64(pte, addr);
#else
- iowrite32((u32)pte, addr);
- iowrite32(pte >> 32, addr + 4);
+ GTT_WRITE32((u32)pte, addr);
+ GTT_WRITE32(pte >> 32, addr + 4);
#endif
}
@@ -1392,7 +1393,7 @@ static void gen8_ggtt_insert_entries(struct
i915_address_space *vm,
addr = sg_dma_address(sg_iter.sg) +
(sg_iter.sg_pgoffset << PAGE_SHIFT);
gen8_set_pte(>t_entries[i],
- gen8_pte_encode(addr, level, true));
+ gen8_pte_encode(addr, level, true), dev_priv);
i++;
}
@@ -1404,7 +1405,7 @@ static void gen8_ggtt_insert_entries(struct
i915_address_space *vm,
* hardware should work, we must keep this posting read for paranoia.
*/
if (i != 0)
- WARN_ON(readq(>t_entries[i-1])
+ WARN_ON(GTT_READ64(>t_entries[i-1])
!= gen8_pte_encode(addr, level, true));
/* This next bit makes the above posting read even more important. We
@@ -1436,7 +1437,8 @@ static void gen6_ggtt_insert_entries(struct
i915_address_space *vm,
for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
addr = sg_page_iter_dma_address(&sg_iter);
- iowrite32(vm->pte_encode(addr, level, true, flags),
>t_entries[i]);
+ GTT_WRITE32(vm->pte_encode(addr, level, true, flags),
+ >t_entries[i]);
i++;
}
@@ -1447,7 +1449,7 @@ static void gen6_ggtt_insert_entries(struct
i915_address_space *vm,
* hardware should work, we must keep this posting read for paranoia.
*/
if (i != 0) {
- unsigned long gtt = readl(>t_entries[i-1]);
+ unsigned long gtt = GTT_READ32(>t_entries[i-1]);
WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
}
@@ -1481,8 +1483,8 @@ static void gen8_ggtt_clear_range(struct
i915_address_space *vm,
I915_CACHE_LLC,
use_scratch);
for (i = 0; i < num_entries; i++)
- gen8_set_pte(>t_base[i], scratch_pte);
- readl(gtt_base);
+ gen8_set_pte(>t_base[i], scratch_pte, dev_priv);
+ GTT_READ32(gtt_base);
}
static void gen6_ggtt_clear_range(struct i915_address_space *vm,
@@ -1506,11 +1508,10 @@ static void gen6_ggtt_clear_range(struct
i915_address_space *vm,
scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC,
use_scratch, 0);
for (i = 0; i < num_entries; i++)
- iowrite32(scratch_pte, >t_base[i]);
- readl(gtt_base);
+ GTT_WRITE32(scratch_pte, >t_base[i]);
+ GTT_READ32(gtt_base);
}
-
static void i915_ggtt_bind_vma(struct i915_vma *vma,
enum i915_cache_level cache_level,
u32 unused)
--
1.9.1
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