[Intel-gfx] [PATCH 47/53] drm/i915: Update ironlake_enable_rc6() to do explicit request management

[John . C . Harrison]

From: John Harrison <john.c.harri...@intel.com>

Updated ironlake_enable_rc6() to do explicit request creation and submission.

v2: Fixed null context bug.

For: VIZ-5115
Signed-off-by: John Harrison <john.c.harri...@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c |   31 +++++++++++++++++++++----------
 1 file changed, 21 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f7c9938..6594a52 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4985,6 +4985,7 @@ static void ironlake_enable_rc6(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_engine_cs *ring = &dev_priv->ring[RCS];
+       struct drm_i915_gem_request *req = NULL;
        bool was_interruptible;
        int ret;
 
@@ -5003,16 +5004,17 @@ static void ironlake_enable_rc6(struct drm_device *dev)
        was_interruptible = dev_priv->mm.interruptible;
        dev_priv->mm.interruptible = false;
 
+       ret = dev_priv->gt.alloc_request(ring, ring->default_context, &req);
+       if (ret)
+               goto err;
+
        /*
         * GPU can automatically power down the render unit if given a page
         * to save state.
         */
        ret = intel_ring_begin(ring, 6);
-       if (ret) {
-               ironlake_teardown_rc6(dev);
-               dev_priv->mm.interruptible = was_interruptible;
-               return;
-       }
+       if (ret)
+               goto err;
 
        intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
        intel_ring_emit(ring, MI_SET_CONTEXT);
@@ -5026,6 +5028,11 @@ static void ironlake_enable_rc6(struct drm_device *dev)
        intel_ring_emit(ring, MI_FLUSH);
        intel_ring_advance(ring);
 
+       ret = i915_add_request_no_flush(req);
+       if (ret)
+               goto err;
+       req = NULL;
+
        /*
         * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
         * does an implicit flush, combined with MI_FLUSH above, it should be
@@ -5033,16 +5040,20 @@ static void ironlake_enable_rc6(struct drm_device *dev)
         */
        ret = intel_ring_idle(ring);
        dev_priv->mm.interruptible = was_interruptible;
-       if (ret) {
-               DRM_ERROR("failed to enable ironlake power savings\n");
-               ironlake_teardown_rc6(dev);
-               return;
-       }
+       if (ret)
+               goto err;
 
        I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | 
PWRCTX_EN);
        I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
 
        intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
+
+err:
+       DRM_ERROR("failed to enable ironlake power savings\n");
+       ironlake_teardown_rc6(dev);
+       dev_priv->mm.interruptible = was_interruptible;
+       if (req)
+               i915_gem_request_unreference(req);
 }
 
 static unsigned long intel_pxfreq(u32 vidfreq)
-- 
1.7.9.5

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