From: Ville Syrjälä <ville.syrj...@linux.intel.com>

Here's an updated version of the series to redo the VLV/CHV watermark
code. The most important thing is that this makes the display stable
on BSW with the fancy new memory PM features enabled by the firmware.

Changes since v1:
* Drop the two plane maxfifo mode patch (Vijay)
* Move one the misplaced hunk to the right patch (Jesse)
* Use the right amount of PFI credits for the cdclk<czclk case (Vijay)
* Drop the extra drain latency multipler frobbing as it no longer
  seems to be necessary to get a stable picture with multiple 4k
  displays. Not really sure if this was due to a BIOS update or what.
* Use plane->state->fb instead of plane->fb in the wm/ddl calculations.
* Don't break VLV maxfifo enable/disable. Noticed this one myself while
  going through the patches

I'm still missing a review on
"drm/i915: Rewrite VLV/CHV watermark code" and "drm/i915: Disable DDR DVFS on 
CHV"
The rest have r-bs now. I kept Jesses r-b on "drm/i915: Pass plane to
vlv_compute_drain_latency()" even though v2 is a slightly different that
v1 due to the plane->state changes.

Vidya Srinivas (1):
  drm/i915: Program PFI credits for VLV

Ville Syrjälä (11):
  drm/i915: Reduce CHV DDL multiplier to 16/8
  drm/i915: Kill DRAIN_LATENCY_PRECISION_* defines
  drm/i915: Simplify VLV drain latency computation
  drm/i915: Hide VLV DDL precision handling
  drm/i915: Reorganize VLV DDL setup
  drm/i915: Pass plane to vlv_compute_drain_latency()
  drm/i915: Read out display FIFO size on VLV/CHV
  drm/i915: Make sure PND deadline mode is enabled on VLV/CHV
  drm/i915: Rewrite VLV/CHV watermark code
  drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV
  drm/i915: Disable DDR DVFS on CHV

 drivers/gpu/drm/i915/i915_drv.h      |  20 ++
 drivers/gpu/drm/i915/i915_reg.h      |  39 ++-
 drivers/gpu/drm/i915/intel_display.c |  38 +++
 drivers/gpu/drm/i915/intel_pm.c      | 577 +++++++++++++++++++++--------------
 4 files changed, 432 insertions(+), 242 deletions(-)

-- 
2.0.5

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