On ti, 2015-03-17 at 15:45 +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
>
> v2: Pass in rotation info to sprite plane updates as well.
>
> v3: Use helper to determine 90/270 rotation. (Michel Thierry)
>
> v4: Rebased for fb modifiers and atomic changes.
>
> For: VIZ-4546
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
> Reviewed-by: Michel Thierry <michel.thie...@intel.com> (v3)
Reviewed-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com> (v4)
> ---
> drivers/gpu/drm/i915/intel_display.c | 27 +++++++++++++++++++++++----
> drivers/gpu/drm/i915/intel_drv.h | 4 ++++
> drivers/gpu/drm/i915/intel_pm.c | 18 +++++++++++++++++-
> drivers/gpu/drm/i915/intel_sprite.c | 5 +----
> 4 files changed, 45 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 9af73b1..19bec33 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11994,6 +11994,28 @@ static void intel_shared_dpll_init(struct drm_device
> *dev)
> }
>
> /**
> + * intel_wm_need_update - Check whether watermarks need updating
> + * @plane: drm plane
> + * @state: new plane state
> + *
> + * Check current plane state versus the new one to determine whether
> + * watermarks need to be recalculated.
> + *
> + * Returns true or false.
> + */
> +bool intel_wm_need_update(struct drm_plane *plane,
> + struct drm_plane_state *state)
> +{
> + /* Update watermarks on tiling changes. */
> + if (!plane->state->fb || !state->fb ||
> + plane->state->fb->modifier[0] != state->fb->modifier[0] ||
> + plane->state->rotation != state->rotation)
> + return true;
> +
> + return false;
> +}
> +
> +/**
> * intel_prepare_plane_fb - Prepare fb for usage on plane
> * @plane: drm plane to prepare for
> * @fb: framebuffer to prepare for presentation
> @@ -12139,10 +12161,7 @@ intel_check_primary_plane(struct drm_plane *plane,
>
> intel_crtc->atomic.update_fbc = true;
>
> - /* Update watermarks on tiling changes. */
> - if (!plane->state->fb || !state->base.fb ||
> - plane->state->fb->modifier[0] !=
> - state->base.fb->modifier[0])
> + if (intel_wm_need_update(plane, &state->base))
> intel_crtc->atomic.update_wm = true;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index ae28fb4..a7ecf95 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -501,6 +501,7 @@ struct intel_plane_wm_parameters {
> bool enabled;
> bool scaled;
> u64 tiling;
> + unsigned int rotation;
> };
>
> struct intel_plane {
> @@ -997,6 +998,9 @@ intel_rotation_90_or_270(unsigned int rotation)
> return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
> }
>
> +bool intel_wm_need_update(struct drm_plane *plane,
> + struct drm_plane_state *state);
> +
> /* shared dpll functions */
> struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
> void assert_shared_dpll(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 288c9d2..4e080a6 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2840,6 +2840,7 @@ static void skl_compute_wm_pipe_parameters(struct
> drm_crtc *crtc,
> }
> p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
> p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
> + p->plane[0].rotation = crtc->primary->state->rotation;
>
> fb = crtc->cursor->state->fb;
> if (fb) {
> @@ -2897,7 +2898,21 @@ static bool skl_compute_plane_wm(const struct
> drm_i915_private *dev_priv,
>
> if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
> p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
> - uint32_t y_tile_minimum = plane_blocks_per_line * 4;
> + uint32_t min_scanlines = 4;
> + uint32_t y_tile_minimum;
> + if (intel_rotation_90_or_270(p_params->rotation)) {
> + switch (p_params->bytes_per_pixel) {
> + case 1:
> + min_scanlines = 16;
> + break;
> + case 2:
> + min_scanlines = 8;
> + break;
> + case 8:
> + WARN(1, "Unsupported pixel depth for rotation");
> + };
> + }
> + y_tile_minimum = plane_blocks_per_line * min_scanlines;
> selected_result = max(method2, y_tile_minimum);
> } else {
> if ((ddb_allocation / plane_blocks_per_line) >= 1)
> @@ -3357,6 +3372,7 @@ skl_update_sprite_wm(struct drm_plane *plane, struct
> drm_crtc *crtc,
> */
> if (fb)
> intel_plane->wm.tiling = fb->modifier[0];
> + intel_plane->wm.rotation = plane->state->rotation;
>
> skl_update_wm(crtc);
> }
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index d960572..b919b0a 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1260,10 +1260,7 @@ finish:
> if (!intel_crtc->primary_enabled && !state->hides_primary)
> intel_crtc->atomic.post_enable_primary = true;
>
> - /* Update watermarks on tiling changes. */
> - if (!plane->state->fb || !state->base.fb ||
> - plane->state->fb->modifier[0] !=
> - state->base.fb->modifier[0])
> + if (intel_wm_need_update(plane, &state->base))
> intel_crtc->atomic.update_wm = true;
> }
>
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