Reviewed-by: Antti Koskipää <antti.koski...@linux.intel.com>
On 03/17/2015 11:39 AM, Imre Deak wrote:
> From: Sumit Singh <sumit.k.si...@intel.com>
>
> The caching options for page table entries have remained the same as
> Cherryview. This patch fixes it so the right code path is taken on BXT.
>
> v2: Fix up commit message (Mike)
>
> Signed-off-by: Sumit Singh <sumit.k.si...@intel.com>
> Signed-off-by: Damien Lespiau <damien.lesp...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index f1b9ea6..4311292 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1506,7 +1506,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device
> *dev)
>
>
> if (INTEL_INFO(dev)->gen >= 8) {
> - if (IS_CHERRYVIEW(dev))
> + if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
> chv_setup_private_ppat(dev_priv);
> else
> bdw_setup_private_ppat(dev_priv);
> @@ -2187,7 +2187,7 @@ static int gen8_gmch_probe(struct drm_device *dev,
>
> *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
>
> - if (IS_CHERRYVIEW(dev))
> + if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
> chv_setup_private_ppat(dev_priv);
> else
> bdw_setup_private_ppat(dev_priv);
>
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