From: Alex Dai <yu....@intel.com>
All gem objects used by GuC are pinned to ggtt space out of range
[0, WOPCM size]. In GuC address space mapping, [0, WPOCM size] is
used internally for its Boot ROM, SRAM etc. Currently this WPOCM
size is 512K. This is done by using of PIN_OFFSET_BIAS.
Issue: VIZ-4884
Signed-off-by: Alex Dai <yu....@intel.com>
---
drivers/gpu/drm/i915/intel_guc.h | 3 ++
drivers/gpu/drm/i915/intel_guc_loader.c | 55 +++++++++++++++++++++++++++++++++
2 files changed, 58 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 0a73122..6b2b5bf 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -99,5 +99,8 @@ struct intel_guc {
extern int intel_guc_load_ucode(struct drm_device *dev, bool wait);
extern void intel_guc_ucode_fini(struct drm_device *dev);
extern void intel_guc_ucode_init(struct drm_device *dev);
+struct drm_i915_gem_object *
+intel_guc_allocate_gem_obj(struct drm_device *dev, u32 size);
+void intel_guc_release_gem_obj(struct drm_i915_gem_object *obj);
#endif
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 45d099f..d37fa42 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -40,6 +40,12 @@
* The firmware installation package will install (symbolic link) proper
version
* of firmware.
*
+ * GuC address space:
+ * GuC does not allow any gfx GGTT address that falls into range [0,
WOPCM_TOP),
+ * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address
is
+ * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
+ * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
+ *
*/
#define I915_GUC_UCODE_GEN8 "i915/guc_gen8.bin"
@@ -47,6 +53,55 @@
MODULE_FIRMWARE(I915_GUC_UCODE_GEN8);
MODULE_FIRMWARE(I915_GUC_UCODE_GEN9);
+/**
+ * intel_guc_allocate_gem_obj() - Allocate gem object for GuC usage
+ * @dev: drm device
+ * @size: size of object
+ *
+ * This is a wrapper to create a gem obj. In order to use it inside GuC, the
+ * object needs to be pinned lifetime. Also we must pin it to gtt space other
+ * than [0, GUC_WOPCM_SIZE] because this range is reserved inside GuC.
+ *
+ * Return: A drm_i915_gem_object if successful, otherwise NULL.
+ */
+struct drm_i915_gem_object *
+intel_guc_allocate_gem_obj(struct drm_device *dev, u32 size)
+{
+ struct drm_i915_gem_object *obj;
+
+ obj = i915_gem_alloc_object(dev, size);
+ if (!obj)
+ return NULL;
+
+ if (i915_gem_object_get_pages(obj)) {
+ drm_gem_object_unreference(&obj->base);
+ return NULL;
+ }
+
+ if (i915_gem_obj_ggtt_pin(obj, PAGE_SIZE,
+ PIN_OFFSET_BIAS | GUC_WOPCM_SIZE_VALUE)) {
+ drm_gem_object_unreference(&obj->base);
+ return NULL;
+ }
+
+ return obj;
+}
+
+/**
+ * intel_guc_release_gem_obj() - Release gem object allocated for GuC usage
+ * @obj: gem obj to be released
+ */
+void intel_guc_release_gem_obj(struct drm_i915_gem_object *obj)
+{
+ if (!obj)
+ return;
+
+ if (i915_gem_obj_is_pinned(obj))
+ i915_gem_object_ggtt_unpin(obj);
+
+ drm_gem_object_unreference(&obj->base);
+}
+
/* Read GuC status register (GUC_STATUS)
* Return true if get a success code from normal boot or RC6 boot
*/
--
1.9.1
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