Combined Valleyview, Haswell and Broadwell '*_modeset_global_pipes()' into one function 'intel_modeset_global_pipes()'
v2: - we don't modify 'disable_pipes', so passing this as a pointer is removed (based on Ville's comment) - introduced a new function 'intel_calc_cdclk()' that combines routines from 'valleyview_calc_cdclk()' and 'haswell_calc_cdclk()' v3: - Let's take a step back and not remove the routines 'valleyview_calc_cdclk()' and 'haswell_calc_cdclk()' from newly introduced routine 'intel_calc_cdclk()' (based on Ville's comment) Signed-off-by: Mika Kahola <mika.kah...@intel.com> --- drivers/gpu/drm/i915/intel_display.c | 63 ++++++++++++++++++------------------ 1 file changed, 32 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 7b97907..f05bd12 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5225,22 +5225,6 @@ static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) return max_pixclk; } -static void valleyview_modeset_global_pipes(struct drm_device *dev, - unsigned *prepare_pipes) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - struct intel_crtc *intel_crtc; - int max_pixclk = intel_mode_max_pixclk(dev_priv); - - if (valleyview_calc_cdclk(dev_priv, max_pixclk) == dev_priv->cdclk_freq) - return; - - /* disable/enable all currently active pipes while we change cdclk */ - for_each_intel_crtc(dev, intel_crtc) - if (intel_crtc->base.state->enable) - *prepare_pipes |= (1 << intel_crtc->pipe); -} - static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) { unsigned int credits, default_credits; @@ -8787,21 +8771,46 @@ static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) cdclk, dev_priv->cdclk_freq); } -static void haswell_modeset_global_pipes(struct drm_device *dev, - unsigned *prepare_pipes) +static int intel_calc_cdclk(struct drm_device *dev, int max_pixclk) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + int cdclk; + + if (IS_VALLEYVIEW(dev)) + cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); + else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) + cdclk = haswell_calc_cdclk(dev_priv, max_pixclk); + + return cdclk; +} + +static void intel_modeset_global_pipes(struct drm_device *dev, + unsigned *prepare_pipes, + unsigned disable_pipes) { struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *crtc; - int max_pixel_rate = ilk_max_pixel_rate(dev_priv); + int max_pixclk; - if (haswell_calc_cdclk(dev_priv, max_pixel_rate) == - dev_priv->cdclk_freq) + /* this modeset is valid only for VLV, HSW, and BDW */ + if (!IS_VALLEYVIEW(dev) && !IS_HASWELL(dev) && !IS_BROADWELL(dev)) + return; + + if (IS_VALLEYVIEW(dev)) + max_pixclk = intel_mode_max_pixclk(dev_priv); + else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) + max_pixclk = ilk_max_pixel_rate(dev_priv); + + if (intel_calc_cdclk(dev, max_pixclk) == dev_priv->cdclk_freq) return; /* disable/enable all currently active pipes while we change cdclk */ for_each_intel_crtc(dev, crtc) - if (crtc->base.enabled) + if (crtc->base.state->enable) *prepare_pipes |= 1 << crtc->pipe; + + /* may have added more to prepare_pipes than we should */ + *prepare_pipes &= ~disable_pipes; } static void haswell_modeset_global_resources(struct drm_atomic_state *state) @@ -11933,15 +11942,7 @@ static int __intel_set_mode(struct drm_crtc *crtc, * mode set on this crtc. For other crtcs we need to use the * adjusted_mode bits in the crtc directly. */ - if (IS_VALLEYVIEW(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) { - if (IS_VALLEYVIEW(dev)) - valleyview_modeset_global_pipes(dev, &prepare_pipes); - else - haswell_modeset_global_pipes(dev, &prepare_pipes); - - /* may have added more to prepare_pipes than we should */ - prepare_pipes &= ~disable_pipes; - } + intel_modeset_global_pipes(dev, &prepare_pipes, disable_pipes); ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes); if (ret) -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx