On Mon, May 11, 2015 at 04:24:59PM +0200, Maarten Lankhorst wrote:
> This removes a lot of users for crtc->config.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankho...@linux.intel.com>
Changing connector->set_dpms should be a separate patch. Otherwise same
comment as with the previous patch about touching _enable functions.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_crt.c | 21 ++++++----
> drivers/gpu/drm/i915/intel_ddi.c | 78
> +++++++++++++++++++++---------------
> drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++-------
> drivers/gpu/drm/i915/intel_dp.c | 49 +++++++++-------------
> drivers/gpu/drm/i915/intel_dp_mst.c | 9 +++--
> drivers/gpu/drm/i915/intel_drv.h | 13 +++---
> drivers/gpu/drm/i915/intel_dsi.c | 11 +++--
> drivers/gpu/drm/i915/intel_dvo.c | 15 ++++---
> drivers/gpu/drm/i915/intel_hdmi.c | 20 +++++----
> drivers/gpu/drm/i915/intel_lvds.c | 11 +++--
> drivers/gpu/drm/i915/intel_sdvo.c | 3 +-
> drivers/gpu/drm/i915/intel_tv.c | 3 +-
> 12 files changed, 150 insertions(+), 119 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_crt.c
> b/drivers/gpu/drm/i915/intel_crt.c
> index 93bb5159d093..d94f6cb91d42 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -152,13 +152,13 @@ static void hsw_crt_pre_enable(struct intel_encoder
> *encoder)
>
> /* Note: The caller is required to filter out dpms modes not supported by the
> * platform. */
> -static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
> +static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode,
> + struct drm_display_mode *adjusted_mode)
> {
> struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crt *crt = intel_encoder_to_crt(encoder);
> struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
> - struct drm_display_mode *adjusted_mode =
> &crtc->config->base.adjusted_mode;
> u32 adpa;
>
> if (INTEL_INFO(dev)->gen >= 5)
> @@ -202,13 +202,16 @@ static void intel_crt_set_dpms(struct intel_encoder
> *encoder, int mode)
> I915_WRITE(crt->adpa_reg, adpa);
> }
>
> -static void intel_disable_crt(struct intel_encoder *encoder)
> +static void intel_disable_crt(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config)
> {
> - intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);
> + intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF,
> + &pipe_config->base.adjusted_mode);
> }
>
>
> -static void hsw_crt_post_disable(struct intel_encoder *encoder)
> +static void hsw_crt_post_disable(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config)
> {
> struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -224,8 +227,10 @@ static void hsw_crt_post_disable(struct intel_encoder
> *encoder)
> static void intel_enable_crt(struct intel_encoder *encoder)
> {
> struct intel_crt *crt = intel_encoder_to_crt(encoder);
> + struct drm_crtc *crtc = encoder->base.crtc;
>
> - intel_crt_set_dpms(encoder, crt->connector->base.dpms);
> + intel_crt_set_dpms(encoder, crt->connector->base.dpms,
> + &crtc->state->adjusted_mode);
> }
>
> /* Special dpms function to support cloning between dvo/sdvo/crt. */
> @@ -265,9 +270,9 @@ static void intel_crt_dpms(struct drm_connector
> *connector, int mode)
> /* From off to on, enable the pipe first. */
> intel_crtc_update_dpms(crtc);
>
> - intel_crt_set_dpms(encoder, mode);
> + intel_crt_set_dpms(encoder, mode, &crtc->state->adjusted_mode);
> } else {
> - intel_crt_set_dpms(encoder, mode);
> + intel_crt_set_dpms(encoder, mode, &crtc->state->adjusted_mode);
>
> intel_crtc_update_dpms(crtc);
> }
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 807e15d41a1b..c5a9e36d6a0e 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -430,7 +430,8 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
> {
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> + struct intel_crtc_state *pipe_config =
> + to_intel_crtc_state(crtc->state);
> u32 temp, i, rx_ctl_val;
>
> /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
> @@ -447,7 +448,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
> /* Enable the PCH Receiver FDI PLL */
> rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
> FDI_RX_PLL_ENABLE |
> - FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
> + FDI_DP_PORT_WIDTH(pipe_config->fdi_lanes);
> I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
> POSTING_READ(_FDI_RXA_CTL);
> udelay(220);
> @@ -457,8 +458,8 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
> I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
>
> /* Configure Port Clock Select */
> - I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
> - WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
> + I915_WRITE(PORT_CLK_SEL(PORT_E), pipe_config->ddi_pll_sel);
> + WARN_ON(pipe_config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
>
> /* Start the training iterating through available voltages and emphasis,
> * testing each value twice. */
> @@ -476,7 +477,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
> * port reversal bit */
> I915_WRITE(DDI_BUF_CTL(PORT_E),
> DDI_BUF_CTL_ENABLE |
> - ((intel_crtc->config->fdi_lanes - 1) << 1) |
> + ((pipe_config->fdi_lanes - 1) << 1) |
> DDI_BUF_TRANS_SELECT(i / 2));
> POSTING_READ(DDI_BUF_CTL(PORT_E));
>
> @@ -1481,15 +1482,16 @@ bool intel_ddi_pll_select(struct intel_crtc
> *intel_crtc,
> void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
> - enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> + struct intel_crtc_state *pipe_config =
> + to_intel_crtc_state(crtc->state);
> + enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> int type = intel_encoder->type;
> uint32_t temp;
>
> if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
> type == INTEL_OUTPUT_DP_MST) {
> temp = TRANS_MSA_SYNC_CLK;
> - switch (intel_crtc->config->pipe_bpp) {
> + switch (pipe_config->pipe_bpp) {
> case 18:
> temp |= TRANS_MSA_6_BPC;
> break;
> @@ -1509,12 +1511,12 @@ void intel_ddi_set_pipe_settings(struct drm_crtc
> *crtc)
> }
> }
>
> -void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
> +void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc,
> + enum transcoder cpu_transcoder,
> + bool state)
> {
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> uint32_t temp;
> temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
> if (state == true)
> @@ -1532,7 +1534,8 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc
> *crtc)
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> enum pipe pipe = intel_crtc->pipe;
> - enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> + struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state);
> + enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> enum port port = intel_ddi_get_encoder_port(intel_encoder);
> int type = intel_encoder->type;
> uint32_t temp;
> @@ -1541,7 +1544,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc
> *crtc)
> temp = TRANS_DDI_FUNC_ENABLE;
> temp |= TRANS_DDI_SELECT_PORT(port);
>
> - switch (intel_crtc->config->pipe_bpp) {
> + switch (pipe_config->pipe_bpp) {
> case 18:
> temp |= TRANS_DDI_BPC_6;
> break;
> @@ -1558,9 +1561,9 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc
> *crtc)
> BUG();
> }
>
> - if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
> + if (pipe_config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
> temp |= TRANS_DDI_PVSYNC;
> - if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
> + if (pipe_config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
> temp |= TRANS_DDI_PHSYNC;
>
> if (cpu_transcoder == TRANSCODER_EDP) {
> @@ -1571,8 +1574,8 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc
> *crtc)
> * using motion blur mitigation (which we don't
> * support). */
> if (IS_HASWELL(dev) &&
> - (intel_crtc->config->pch_pfit.enabled ||
> - intel_crtc->config->pch_pfit.force_thru))
> + (pipe_config->pch_pfit.enabled ||
> + pipe_config->pch_pfit.force_thru))
> temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
> else
> temp |= TRANS_DDI_EDP_INPUT_A_ON;
> @@ -1590,14 +1593,14 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc
> *crtc)
> }
>
> if (type == INTEL_OUTPUT_HDMI) {
> - if (intel_crtc->config->has_hdmi_sink)
> + if (pipe_config->has_hdmi_sink)
> temp |= TRANS_DDI_MODE_SELECT_HDMI;
> else
> temp |= TRANS_DDI_MODE_SELECT_DVI;
>
> } else if (type == INTEL_OUTPUT_ANALOG) {
> temp |= TRANS_DDI_MODE_SELECT_FDI;
> - temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
> + temp |= (pipe_config->fdi_lanes - 1) << 1;
>
> } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
> type == INTEL_OUTPUT_EDP) {
> @@ -1747,17 +1750,19 @@ void intel_ddi_enable_pipe_clock(struct intel_crtc
> *intel_crtc)
> struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
> enum port port = intel_ddi_get_encoder_port(intel_encoder);
> - enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> + struct intel_crtc_state *pipe_config =
> + to_intel_crtc_state(crtc->state);
> + enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
>
> if (cpu_transcoder != TRANSCODER_EDP)
> I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
> TRANS_CLK_SEL_PORT(port));
> }
>
> -void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
> +void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc,
> + enum transcoder cpu_transcoder)
> {
> struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
> - enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
>
> if (cpu_transcoder != TRANSCODER_EDP)
> I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
> @@ -1902,7 +1907,8 @@ static void intel_ddi_pre_enable(struct intel_encoder
> *intel_encoder)
> }
> }
>
> -static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
> +static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
> + struct intel_crtc_state *pipe_config)
> {
> struct drm_encoder *encoder = &intel_encoder->base;
> struct drm_device *dev = encoder->dev;
> @@ -1945,10 +1951,11 @@ static void intel_enable_ddi(struct intel_encoder
> *intel_encoder)
> {
> struct drm_encoder *encoder = &intel_encoder->base;
> struct drm_crtc *crtc = encoder->crtc;
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct drm_device *dev = encoder->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> enum port port = intel_ddi_get_encoder_port(intel_encoder);
> + struct intel_crtc_state *pipe_config =
> + to_intel_crtc_state(crtc->state);
> int type = intel_encoder->type;
>
> if (type == INTEL_OUTPUT_HDMI) {
> @@ -1970,25 +1977,28 @@ static void intel_enable_ddi(struct intel_encoder
> *intel_encoder)
>
> intel_edp_backlight_on(intel_dp);
> intel_psr_enable(intel_dp);
> - intel_edp_drrs_enable(intel_dp);
> +
> + if (pipe_config->has_drrs)
> + intel_edp_drrs_enable(intel_dp);
> + else
> + DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
> }
>
> - if (intel_crtc->config->has_audio) {
> + if (pipe_config->has_audio) {
> intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
> intel_audio_codec_enable(intel_encoder);
> }
> }
>
> -static void intel_disable_ddi(struct intel_encoder *intel_encoder)
> +static void intel_disable_ddi(struct intel_encoder *intel_encoder,
> + struct intel_crtc_state *pipe_config)
> {
> struct drm_encoder *encoder = &intel_encoder->base;
> - struct drm_crtc *crtc = encoder->crtc;
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> int type = intel_encoder->type;
> struct drm_device *dev = encoder->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> - if (intel_crtc->config->has_audio) {
> + if (pipe_config->has_audio) {
> intel_audio_codec_disable(intel_encoder);
> intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
> }
> @@ -1996,7 +2006,8 @@ static void intel_disable_ddi(struct intel_encoder
> *intel_encoder)
> if (type == INTEL_OUTPUT_EDP) {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>
> - intel_edp_drrs_disable(intel_dp);
> + if (pipe_config->has_drrs)
> + intel_edp_drrs_disable(intel_dp);
> intel_psr_disable(intel_dp);
> intel_edp_backlight_off(intel_dp);
> }
> @@ -2546,13 +2557,14 @@ void intel_ddi_prepare_link_retrain(struct
> drm_encoder *encoder)
> udelay(600);
> }
>
> -void intel_ddi_fdi_disable(struct drm_crtc *crtc)
> +void intel_ddi_fdi_disable(struct drm_crtc *crtc,
> + struct intel_crtc_state *old_state)
> {
> struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
> uint32_t val;
>
> - intel_ddi_post_disable(intel_encoder);
> + intel_ddi_post_disable(intel_encoder, old_state);
>
> val = I915_READ(_FDI_RXA_CTL);
> val &= ~FDI_RX_ENABLE;
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 311a4b44bebe..7bc78b49f9f4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4953,7 +4953,9 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
> lpt_pch_enable(crtc);
>
> if (intel_crtc->config->dp_encoder_is_mst)
> - intel_ddi_set_vc_payload_alloc(crtc, true);
> + intel_ddi_set_vc_payload_alloc(crtc,
> + pipe_config->cpu_transcoder,
> + true);
>
> assert_vblank_disabled(crtc);
> drm_crtc_vblank_on(crtc);
> @@ -4994,7 +4996,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc,
> u32 reg, temp;
>
> for_each_encoder_on_crtc(dev, crtc, encoder)
> - encoder->disable(encoder);
> + encoder->disable(encoder, old_state);
>
> drm_crtc_vblank_off(crtc);
> assert_vblank_disabled(crtc);
> @@ -5008,7 +5010,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc,
>
> for_each_encoder_on_crtc(dev, crtc, encoder)
> if (encoder->post_disable)
> - encoder->post_disable(encoder);
> + encoder->post_disable(encoder, old_state);
>
> if (old_state->has_pch_encoder) {
> ironlake_fdi_disable(crtc);
> @@ -5045,7 +5047,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc,
>
> for_each_encoder_on_crtc(dev, crtc, encoder) {
> intel_opregion_notify_encoder(encoder, false);
> - encoder->disable(encoder);
> + encoder->disable(encoder, old_state);
> }
>
> drm_crtc_vblank_off(crtc);
> @@ -5057,7 +5059,9 @@ static void haswell_crtc_disable(struct drm_crtc *crtc,
> intel_disable_pipe(intel_crtc, old_state);
>
> if (intel_crtc->config->dp_encoder_is_mst)
> - intel_ddi_set_vc_payload_alloc(crtc, false);
> + intel_ddi_set_vc_payload_alloc(crtc,
> + old_state->cpu_transcoder,
> + false);
>
> intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
>
> @@ -5068,16 +5072,16 @@ static void haswell_crtc_disable(struct drm_crtc
> *crtc,
> else
> MISSING_CASE(INTEL_INFO(dev)->gen);
>
> - intel_ddi_disable_pipe_clock(intel_crtc);
> + intel_ddi_disable_pipe_clock(intel_crtc, old_state->cpu_transcoder);
>
> if (intel_crtc->config->has_pch_encoder) {
> lpt_disable_pch_transcoder(dev_priv);
> - intel_ddi_fdi_disable(crtc);
> + intel_ddi_fdi_disable(crtc, old_state);
> }
>
> for_each_encoder_on_crtc(dev, crtc, encoder)
> if (encoder->post_disable)
> - encoder->post_disable(encoder);
> + encoder->post_disable(encoder, old_state);
> }
>
> static void i9xx_pfit_enable(struct intel_crtc *crtc,
> @@ -5914,7 +5918,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc,
> intel_wait_for_vblank(dev, pipe);
>
> for_each_encoder_on_crtc(dev, crtc, encoder)
> - encoder->disable(encoder);
> + encoder->disable(encoder, old_state);
>
> drm_crtc_vblank_off(crtc);
> assert_vblank_disabled(crtc);
> @@ -5925,7 +5929,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc,
>
> for_each_encoder_on_crtc(dev, crtc, encoder)
> if (encoder->post_disable)
> - encoder->post_disable(encoder);
> + encoder->post_disable(encoder, old_state);
>
> if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
> if (IS_CHERRYVIEW(dev))
> @@ -14672,12 +14676,12 @@ static void intel_sanitize_encoder(struct
> intel_encoder *encoder)
> {
> struct intel_connector *connector;
> struct drm_device *dev = encoder->base.dev;
> + struct drm_crtc *crtc = encoder->base.crtc;
>
> /* We need to check both for a crtc link (meaning that the
> * encoder is active and trying to read from a pipe) and the
> * pipe itself being active. */
> - bool has_active_crtc = encoder->base.crtc &&
> - to_intel_crtc(encoder->base.crtc)->active;
> + bool has_active_crtc = crtc && to_intel_crtc(crtc)->active;
>
> if (encoder->connectors_active && !has_active_crtc) {
> DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no
> active pipe!\n",
> @@ -14687,13 +14691,15 @@ static void intel_sanitize_encoder(struct
> intel_encoder *encoder)
> /* Connector is active, but has no active pipe. This is
> * fallout from our resume register restoring. Disable
> * the encoder manually again. */
> - if (encoder->base.crtc) {
> + if (crtc) {
> + struct intel_crtc_state *pipe_config =
> + to_intel_crtc_state(crtc->state);
> DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
> encoder->base.base.id,
> encoder->base.name);
> - encoder->disable(encoder);
> + encoder->disable(encoder, pipe_config);
> if (encoder->post_disable)
> - encoder->post_disable(encoder);
> + encoder->post_disable(encoder, pipe_config);
> }
> encoder->base.crtc = NULL;
> encoder->connectors_active = false;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 83de36bfddc1..eda1b22c3111 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1499,17 +1499,19 @@ found:
> static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
> {
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
> - struct drm_device *dev = crtc->base.dev;
> + struct drm_crtc *crtc = dig_port->base.base.crtc;
> + struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_crtc_state *pipe_config =
> + to_intel_crtc_state(crtc->state);
> u32 dpa_ctl;
>
> DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
> - crtc->config->port_clock);
> + pipe_config->port_clock);
> dpa_ctl = I915_READ(DP_A);
> dpa_ctl &= ~DP_PLL_FREQ_MASK;
>
> - if (crtc->config->port_clock == 162000) {
> + if (pipe_config->port_clock == 162000) {
> /* For a long time we've carried around a ILK-DevA w/a for the
> * 160MHz clock. If we're really unlucky, it's still required.
> */
> @@ -2108,7 +2110,8 @@ static void ironlake_edp_pll_on(struct intel_dp
> *intel_dp)
> udelay(200);
> }
>
> -static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
> +static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
> + struct intel_crtc_state *pipe_config)
> {
> struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
> @@ -2117,7 +2120,7 @@ static void ironlake_edp_pll_off(struct intel_dp
> *intel_dp)
> u32 dpa_ctl;
>
> assert_pipe_disabled(dev_priv,
> - to_intel_crtc(crtc)->config->cpu_transcoder,
> + pipe_config->cpu_transcoder,
> to_intel_crtc(crtc)->pipe);
>
> dpa_ctl = I915_READ(DP_A);
> @@ -2308,13 +2311,13 @@ static void intel_dp_get_config(struct intel_encoder
> *encoder,
> }
> }
>
> -static void intel_disable_dp(struct intel_encoder *encoder)
> +static void intel_disable_dp(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config)
> {
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> struct drm_device *dev = encoder->base.dev;
> - struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
>
> - if (crtc->config->has_audio)
> + if (pipe_config->has_audio)
> intel_audio_codec_disable(encoder);
>
> if (HAS_PSR(dev) && !HAS_DDI(dev))
> @@ -2332,24 +2335,27 @@ static void intel_disable_dp(struct intel_encoder
> *encoder)
> intel_dp_link_down(intel_dp);
> }
>
> -static void ilk_post_disable_dp(struct intel_encoder *encoder)
> +static void ilk_post_disable_dp(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config)
> {
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> enum port port = dp_to_dig_port(intel_dp)->port;
>
> intel_dp_link_down(intel_dp);
> if (port == PORT_A)
> - ironlake_edp_pll_off(intel_dp);
> + ironlake_edp_pll_off(intel_dp, pipe_config);
> }
>
> -static void vlv_post_disable_dp(struct intel_encoder *encoder)
> +static void vlv_post_disable_dp(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config)
> {
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
>
> intel_dp_link_down(intel_dp);
> }
>
> -static void chv_post_disable_dp(struct intel_encoder *encoder)
> +static void chv_post_disable_dp(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config)
> {
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> @@ -5249,7 +5255,6 @@ static void intel_dp_set_drrs_state(struct drm_device
> *dev, int refresh_rate)
> struct intel_encoder *encoder;
> struct intel_digital_port *dig_port = NULL;
> struct intel_dp *intel_dp = dev_priv->drrs.dp;
> - struct intel_crtc_state *config = NULL;
> struct intel_crtc *intel_crtc = NULL;
> u32 reg, val;
> enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
> @@ -5278,8 +5283,6 @@ static void intel_dp_set_drrs_state(struct drm_device
> *dev, int refresh_rate)
> return;
> }
>
> - config = intel_crtc->config;
> -
> if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
> DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
> return;
> @@ -5345,14 +5348,6 @@ void intel_edp_drrs_enable(struct intel_dp *intel_dp)
> {
> struct drm_device *dev = intel_dp_to_dev(intel_dp);
> struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - struct drm_crtc *crtc = dig_port->base.base.crtc;
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -
> - if (!intel_crtc->config->has_drrs) {
> - DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
> - return;
> - }
>
> mutex_lock(&dev_priv->drrs.mutex);
> if (WARN_ON(dev_priv->drrs.dp)) {
> @@ -5377,12 +5372,6 @@ void intel_edp_drrs_disable(struct intel_dp *intel_dp)
> {
> struct drm_device *dev = intel_dp_to_dev(intel_dp);
> struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - struct drm_crtc *crtc = dig_port->base.base.crtc;
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -
> - if (!intel_crtc->config->has_drrs)
> - return;
>
> mutex_lock(&dev_priv->drrs.mutex);
> if (!dev_priv->drrs.dp) {
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
> b/drivers/gpu/drm/i915/intel_dp_mst.c
> index 6e4cc5334f47..4992c8025520 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -101,7 +101,8 @@ static bool intel_dp_mst_compute_config(struct
> intel_encoder *encoder,
>
> }
>
> -static void intel_mst_disable_dp(struct intel_encoder *encoder)
> +static void intel_mst_disable_dp(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config)
> {
> struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
> struct intel_digital_port *intel_dig_port = intel_mst->primary;
> @@ -118,7 +119,8 @@ static void intel_mst_disable_dp(struct intel_encoder
> *encoder)
> }
> }
>
> -static void intel_mst_post_disable_dp(struct intel_encoder *encoder)
> +static void intel_mst_post_disable_dp(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config)
> {
> struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
> struct intel_digital_port *intel_dig_port = intel_mst->primary;
> @@ -136,7 +138,8 @@ static void intel_mst_post_disable_dp(struct
> intel_encoder *encoder)
> intel_dp->active_mst_links--;
> intel_mst->port = NULL;
> if (intel_dp->active_mst_links == 0) {
> - intel_dig_port->base.post_disable(&intel_dig_port->base);
> + intel_dig_port->base.post_disable(&intel_dig_port->base,
> + pipe_config);
> intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
> }
> }
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 58240e63630c..eb87f82b5aff 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -141,8 +141,9 @@ struct intel_encoder {
> void (*pre_enable)(struct intel_encoder *);
> void (*enable)(struct intel_encoder *);
> void (*mode_set)(struct intel_encoder *intel_encoder);
> - void (*disable)(struct intel_encoder *);
> - void (*post_disable)(struct intel_encoder *);
> + void (*disable)(struct intel_encoder *, struct intel_crtc_state *);
> + void (*post_disable)(struct intel_encoder *,
> + struct intel_crtc_state *);
> /* Read out the current hw state of this connector, returning true if
> * the encoder is active. If the encoder is enabled it also set the pipe
> * it is connected to in the pipe parameter. */
> @@ -910,13 +911,14 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc
> *crtc);
> void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
> enum transcoder cpu_transcoder);
> void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
> -void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
> +void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc,
> + enum transcoder cpu_transcoder);
> bool intel_ddi_pll_select(struct intel_crtc *crtc,
> struct intel_crtc_state *crtc_state);
> void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
> void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
> bool intel_ddi_connector_get_hw_state(struct intel_connector
> *intel_connector);
> -void intel_ddi_fdi_disable(struct drm_crtc *crtc);
> +void intel_ddi_fdi_disable(struct drm_crtc *crtc, struct intel_crtc_state *);
> void intel_ddi_get_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config);
> struct intel_encoder *
> @@ -925,7 +927,8 @@ intel_ddi_get_crtc_new_encoder(struct intel_crtc_state
> *crtc_state);
> void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
> void intel_ddi_clock_get(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config);
> -void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
> +void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc,
> + enum transcoder, bool state);
> void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
> enum port port, int type);
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> b/drivers/gpu/drm/i915/intel_dsi.c
> index 51966426addf..3f28b046751b 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -409,6 +409,9 @@ static void intel_dsi_pre_enable(struct intel_encoder
> *encoder)
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> + struct intel_crtc_state *pipe_config =
> + to_intel_crtc_state(intel_crtc->base.state);
> +
> enum pipe pipe = intel_crtc->pipe;
> enum port port;
> u32 tmp;
> @@ -422,7 +425,7 @@ static void intel_dsi_pre_enable(struct intel_encoder
> *encoder)
> I915_WRITE(DPLL(pipe), tmp);
>
> /* update the hw state for DPLL */
> - intel_crtc->config->dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV |
> + pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV |
> DPLL_REFA_CLK_ENABLE_VLV;
>
> tmp = I915_READ(DSPCLK_GATE_D);
> @@ -454,7 +457,8 @@ static void intel_dsi_enable_nop(struct intel_encoder
> *encoder)
> */
> }
>
> -static void intel_dsi_pre_disable(struct intel_encoder *encoder)
> +static void intel_dsi_pre_disable(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config)
> {
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> enum port port;
> @@ -556,7 +560,8 @@ static void intel_dsi_clear_device_ready(struct
> intel_encoder *encoder)
> vlv_disable_dsi_pll(encoder);
> }
>
> -static void intel_dsi_post_disable(struct intel_encoder *encoder)
> +static void intel_dsi_post_disable(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config)
> {
> struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> diff --git a/drivers/gpu/drm/i915/intel_dvo.c
> b/drivers/gpu/drm/i915/intel_dvo.c
> index ece5bd754f85..4dac4ce5963a 100644
> --- a/drivers/gpu/drm/i915/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/intel_dvo.c
> @@ -166,7 +166,8 @@ static void intel_dvo_get_config(struct intel_encoder
> *encoder,
> pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
> }
>
> -static void intel_disable_dvo(struct intel_encoder *encoder)
> +static void intel_disable_dvo(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config)
> {
> struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
> @@ -182,13 +183,14 @@ static void intel_enable_dvo(struct intel_encoder
> *encoder)
> {
> struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
> - struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
> + struct drm_crtc *crtc = encoder->base.crtc;
> + struct drm_crtc_state *pipe_config = crtc->state;
> u32 dvo_reg = intel_dvo->dev.dvo_reg;
> u32 temp = I915_READ(dvo_reg);
>
> intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
> - &crtc->config->base.mode,
> - &crtc->config->base.adjusted_mode);
> + &pipe_config->mode,
> + &pipe_config->adjusted_mode);
>
> I915_WRITE(dvo_reg, temp | DVO_ENABLE);
> I915_READ(dvo_reg);
> @@ -201,7 +203,6 @@ static void intel_dvo_dpms(struct drm_connector
> *connector, int mode)
> {
> struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
> struct drm_crtc *crtc;
> - struct intel_crtc_state *config;
>
> /* dvo supports only 2 dpms states. */
> if (mode != DRM_MODE_DPMS_ON)
> @@ -222,8 +223,6 @@ static void intel_dvo_dpms(struct drm_connector
> *connector, int mode)
> /* We call connector dpms manually below in case pipe dpms doesn't
> * change due to cloning. */
> if (mode == DRM_MODE_DPMS_ON) {
> - config = to_intel_crtc(crtc)->config;
> -
> intel_dvo->base.connectors_active = true;
>
> intel_crtc_update_dpms(crtc);
> @@ -296,7 +295,7 @@ static void intel_dvo_pre_enable(struct intel_encoder
> *encoder)
> struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
> - struct drm_display_mode *adjusted_mode =
> &crtc->config->base.adjusted_mode;
> + struct drm_display_mode *adjusted_mode =
> &crtc->base.state->adjusted_mode;
> struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
> int pipe = crtc->pipe;
> u32 dvo_val;
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index d04e6dc97fe5..76994dc033a3 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -866,7 +866,8 @@ static void vlv_enable_hdmi(struct intel_encoder *encoder)
> {
> }
>
> -static void intel_disable_hdmi(struct intel_encoder *encoder)
> +static void intel_disable_hdmi(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config)
> {
> struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -875,7 +876,7 @@ static void intel_disable_hdmi(struct intel_encoder
> *encoder)
> u32 temp;
> u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
>
> - if (crtc->config->has_audio)
> + if (pipe_config->has_audio)
> intel_audio_codec_disable(encoder);
>
> temp = I915_READ(intel_hdmi->hdmi_reg);
> @@ -883,8 +884,7 @@ static void intel_disable_hdmi(struct intel_encoder
> *encoder)
> /* HW workaround for IBX, we need to move the port to transcoder A
> * before disabling it. */
> if (HAS_PCH_IBX(dev)) {
> - struct drm_crtc *crtc = encoder->base.crtc;
> - int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
> + int pipe = crtc ? crtc->pipe : -1;
>
> if (temp & SDVO_PIPE_B_SELECT) {
> temp &= ~SDVO_PIPE_B_SELECT;
> @@ -1426,7 +1426,8 @@ static void chv_hdmi_pre_pll_enable(struct
> intel_encoder *encoder)
> mutex_unlock(&dev_priv->dpio_lock);
> }
>
> -static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
> +static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config)
> {
> struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> @@ -1442,7 +1443,8 @@ static void vlv_hdmi_post_disable(struct intel_encoder
> *encoder)
> mutex_unlock(&dev_priv->dpio_lock);
> }
>
> -static void chv_hdmi_post_disable(struct intel_encoder *encoder)
> +static void chv_hdmi_post_disable(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config)
> {
> struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> struct drm_device *dev = encoder->base.dev;
> @@ -1483,8 +1485,10 @@ static void chv_hdmi_pre_enable(struct intel_encoder
> *encoder)
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *intel_crtc =
> to_intel_crtc(encoder->base.crtc);
> + struct intel_crtc_state *pipe_config =
> + to_intel_crtc_state(intel_crtc->base.state);
> struct drm_display_mode *adjusted_mode =
> - &intel_crtc->config->base.adjusted_mode;
> + &pipe_config->base.adjusted_mode;
> enum dpio_channel ch = vlv_dport_to_channel(dport);
> int pipe = intel_crtc->pipe;
> int data, i, stagger;
> @@ -1636,7 +1640,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder
> *encoder)
> mutex_unlock(&dev_priv->dpio_lock);
>
> intel_hdmi->set_infoframes(&encoder->base,
> - intel_crtc->config->has_hdmi_sink,
> + pipe_config->has_hdmi_sink,
> adjusted_mode);
>
> intel_enable_hdmi(encoder);
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c
> b/drivers/gpu/drm/i915/intel_lvds.c
> index 9a9df0fa67f9..8aaaa24144f0 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -139,8 +139,10 @@ static void intel_pre_enable_lvds(struct intel_encoder
> *encoder)
> struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
> + struct intel_crtc_state *pipe_config =
> + to_intel_crtc_state(crtc->base.state);
> const struct drm_display_mode *adjusted_mode =
> - &crtc->config->base.adjusted_mode;
> + &pipe_config->base.adjusted_mode;
> int pipe = crtc->pipe;
> u32 temp;
>
> @@ -168,7 +170,7 @@ static void intel_pre_enable_lvds(struct intel_encoder
> *encoder)
>
> /* set the corresponsding LVDS_BORDER bit */
> temp &= ~LVDS_BORDER_ENABLE;
> - temp |= crtc->config->gmch_pfit.lvds_border_bits;
> + temp |= pipe_config->gmch_pfit.lvds_border_bits;
> /* Set the B0-B3 data pairs corresponding to whether we're going to
> * set the DPLLs for dual-channel mode or not.
> */
> @@ -191,7 +193,7 @@ static void intel_pre_enable_lvds(struct intel_encoder
> *encoder)
> if (INTEL_INFO(dev)->gen == 4) {
> /* Bspec wording suggests that LVDS port dithering only exists
> * for 18bpp panels. */
> - if (crtc->config->dither && crtc->config->pipe_bpp == 18)
> + if (pipe_config->dither && pipe_config->pipe_bpp == 18)
> temp |= LVDS_ENABLE_DITHER;
> else
> temp &= ~LVDS_ENABLE_DITHER;
> @@ -235,7 +237,8 @@ static void intel_enable_lvds(struct intel_encoder
> *encoder)
> intel_panel_enable_backlight(intel_connector);
> }
>
> -static void intel_disable_lvds(struct intel_encoder *encoder)
> +static void intel_disable_lvds(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config)
> {
> struct drm_device *dev = encoder->base.dev;
> struct intel_lvds_encoder *lvds_encoder =
> to_lvds_encoder(&encoder->base);
> diff --git a/drivers/gpu/drm/i915/intel_sdvo.c
> b/drivers/gpu/drm/i915/intel_sdvo.c
> index 0a0625761f42..6a68098f8b08 100644
> --- a/drivers/gpu/drm/i915/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> @@ -1425,7 +1425,8 @@ static void intel_sdvo_get_config(struct intel_encoder
> *encoder,
> pipe_config->pixel_multiplier, encoder_pixel_multiplier);
> }
>
> -static void intel_disable_sdvo(struct intel_encoder *encoder)
> +static void intel_disable_sdvo(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config)
> {
> struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
> diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
> index b4aeb256128f..9816a9f88ff5 100644
> --- a/drivers/gpu/drm/i915/intel_tv.c
> +++ b/drivers/gpu/drm/i915/intel_tv.c
> @@ -863,7 +863,8 @@ intel_enable_tv(struct intel_encoder *encoder)
> }
>
> static void
> -intel_disable_tv(struct intel_encoder *encoder)
> +intel_disable_tv(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config)
> {
> struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> --
> 2.1.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
