Properly allocate min blocks per hw requirements.
Signed-off-by: Chandra Konduru <chandra.kond...@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 39 +++++++++++++++++++++++++++++++++++++--
1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 32ff034..ea3e435 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2679,6 +2679,41 @@ skl_get_total_relative_data_rate(struct intel_crtc
*intel_crtc,
return total_data_rate;
}
+static uint16_t
+skl_dbuf_min_alloc(const struct intel_plane_wm_parameters *p, int y_plane)
+{
+ uint16_t min_alloc;
+
+ /* For packed formats, no y-plane, return 0 */
+ if (y_plane && !p->y_bytes_per_pixel)
+ return 0;
+
+
+ if (p->tiling == I915_FORMAT_MOD_Y_TILED ||
+ p->tiling == I915_FORMAT_MOD_Yf_TILED) {
+ uint32_t min_scanlines = 8;
+ uint8_t bytes_per_pixel =
+ y_plane ? p->y_bytes_per_pixel : p->bytes_per_pixel;
+
+ switch (bytes_per_pixel) {
+ case 1:
+ min_scanlines = 32;
+ break;
+ case 2:
+ min_scanlines = 16;
+ break;
+ case 8:
+ WARN(1, "Unsupported pixel depth for rotation");
+ }
+ min_alloc = DIV_ROUND_UP((4 * p->horiz_pixels/(y_plane ? 1 : 2)
*
+ bytes_per_pixel), 512) * min_scanlines/4 + 3;
+ } else {
+ min_alloc = 8;
+ }
+
+ return min_alloc;
+}
+
static void
skl_allocate_pipe_ddb(struct drm_crtc *crtc,
const struct intel_wm_config *config,
@@ -2719,9 +2754,9 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc,
if (!p->enabled)
continue;
- minimum[plane] = 8;
+ minimum[plane] = skl_dbuf_min_alloc(p, 0); /*
uv-plane/packed */
alloc_size -= minimum[plane];
- y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
+ y_minimum[plane] = skl_dbuf_min_alloc(p, 1); /* y-plane */
alloc_size -= y_minimum[plane];
}
--
1.7.9.5
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