On Wed, Jul 22, 2015 at 03:36:48PM +0530, Sivakumar Thulasimani wrote:
> From: "Thulasimani,Sivakumar" <sivakumar.thulasim...@intel.com>
> 
> DP spec requires the checksum of the last block read to be written
> when replying to TEST_EDID_READ. This patch fixes the current code
> to do the same.
> 
> Signed-off-by: Sivakumar Thulasimani <sivakumar.thulasim...@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c |   11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index f1b9f93..9617d04 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4090,9 +4090,18 @@ static uint8_t intel_dp_autotest_edid(struct intel_dp 
> *intel_dp)
>                                     intel_dp->aux.i2c_defer_count);
>               intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
>       } else {
> +             struct edid *block = intel_connector->detect_edid;
> +             uint8_t temp = intel_connector->detect_edid->extensions;
> +
> +             /* We have to write the checksum
> +              * of the last block read
> +              */
> +             while (temp--)
> +                     block++;

                block += block->extensions;

instead of implementing addition by adding lots of 1? Also if you want to
simplify computation by extracting local variables, give them a better
name than "temp". That's somewhat ok for a reused u32 tmp for register
read-modify-writes over lots of registers, but not really for anything
else.
-Daniel

> +
>               if (!drm_dp_dpcd_write(&intel_dp->aux,
>                                       DP_TEST_EDID_CHECKSUM,
> -                                     &intel_connector->detect_edid->checksum,
> +                                     &block->checksum,
>                                       1))
>                       DRM_DEBUG_KMS("Failed to write EDID checksum\n");
>  
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Reply via email to