On 08/26/2015 12:58 AM, Jani Nikula wrote:
This is a rebase of [1] and originally [2]. I haven't tried this in a year and I have no idea if it works on SKL, and it's not implemented for BXT. However there's renewed interest, so here's the rebase.
Renewed interest as an ODM has been reporting that BSW is producing an incorrect PWM frequency. This is due to a CHV documentation issue that states the S0IX clock is 25MHz when it's actually only 19.2MHz.
BR, Jani. [1] http://mid.gmane.org/cover.1431003197.git.jani.nik...@intel.com [2] http://mid.gmane.org/cover.1389109881.git.jani.nik...@intel.com Jani Nikula (2): drm/i915: move intel_hrawclk() to intel_display.c drm/i915: initialize backlight max from VBT drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_display.c | 33 ++++++++ drivers/gpu/drm/i915/intel_dp.c | 34 -------- drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_panel.c | 160 +++++++++++++++++++++++++++++++++-- 6 files changed, 190 insertions(+), 41 deletions(-)
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