On 09/18/2015 10:03 AM, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
> 
> The PIPE_FRMCOUNT_GM45 and PIPE_FLIPCOUNT_GM45 names have bothered me
> for a long time. The work equally well for ELK and onwards, so let's
> s/GM45/G4X/.
> 
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c      |  6 +++---
>  drivers/gpu/drm/i915/i915_reg.h      | 12 ++++++------
>  drivers/gpu/drm/i915/intel_display.c |  4 ++--
>  3 files changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 24f68de..4b61a42 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -671,10 +671,10 @@ static u32 i915_get_vblank_counter(struct drm_device 
> *dev, int pipe)
>       return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
>  }
>  
> -static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
> +static u32 g4x_get_vblank_counter(struct drm_device *dev, int pipe)
>  {
>       struct drm_i915_private *dev_priv = dev->dev_private;
> -     int reg = PIPE_FRMCOUNT_GM45(pipe);
> +     int reg = PIPE_FRMCOUNT_G4X(pipe);
>  
>       return I915_READ(reg);
>  }
> @@ -4311,7 +4311,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>               dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
>       } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
>               dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
> -             dev->driver->get_vblank_counter = gm45_get_vblank_counter;
> +             dev->driver->get_vblank_counter = g4x_get_vblank_counter;
>       } else {
>               dev->driver->get_vblank_counter = i915_get_vblank_counter;
>               dev->max_vblank_count = 0xffffff; /* only 24 bits of frame 
> count */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 02f0935..0cc41e4b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4796,10 +4796,10 @@ enum skl_disp_power_wells {
>  #define   PIPE_PIXEL_MASK         0x00ffffff
>  #define   PIPE_PIXEL_SHIFT        0
>  /* GM45+ just has to be different */
> -#define _PIPEA_FRMCOUNT_GM45 0x70040
> -#define _PIPEA_FLIPCOUNT_GM45        0x70044
> -#define PIPE_FRMCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_GM45)
> -#define PIPE_FLIPCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_GM45)
> +#define _PIPEA_FRMCOUNT_G4X  0x70040
> +#define _PIPEA_FLIPCOUNT_G4X 0x70044
> +#define PIPE_FRMCOUNT_G4X(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
> +#define PIPE_FLIPCOUNT_G4X(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
>  
>  /* Cursor A & B regs */
>  #define _CURACNTR            0x70080
> @@ -4962,8 +4962,8 @@ enum skl_disp_power_wells {
>  #define _PIPEBSTAT           (dev_priv->info.display_mmio_offset + 0x71024)
>  #define _PIPEBFRAMEHIGH              0x71040
>  #define _PIPEBFRAMEPIXEL     0x71044
> -#define _PIPEB_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71040)
> -#define _PIPEB_FLIPCOUNT_GM45        (dev_priv->info.display_mmio_offset + 
> 0x71044)
> +#define _PIPEB_FRMCOUNT_G4X  (dev_priv->info.display_mmio_offset + 0x71040)
> +#define _PIPEB_FLIPCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71044)
>  
>  
>  /* Display B control */
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 92e624b..0074781 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10769,7 +10769,7 @@ static bool page_flip_finished(struct intel_crtc 
> *crtc)
>        */
>       return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
>               crtc->unpin_work->gtt_offset &&
> -             
> g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
> +             
> g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
>                                   crtc->unpin_work->flip_count);
>  }
>  
> @@ -11374,7 +11374,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
>       intel_crtc->reset_counter = 
> atomic_read(&dev_priv->gpu_error.reset_counter);
>  
>       if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
> -             work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
> +             work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
>  
>       if (IS_VALLEYVIEW(dev)) {
>               ring = &dev_priv->ring[BCS];
> 

Reviewed-by: Jesse Barnes <jbar...@virtuousgeek.org>
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