On Wed, Nov 04, 2015 at 11:20:10PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
>
> The logical render context population has a bunch of raw ring register
> offsets. Use the names we have for them, and in cases where we we don't,
> give them names.
>
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
> drivers/gpu/drm/i915/intel_lrc.c | 22 +++++++++++-----------
> 2 files changed, 19 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fe36b74..2478267 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1646,8 +1646,16 @@ enum skl_disp_power_wells {
> #define HWSTAM 0x02098
> #define DMA_FADD_I8XX 0x020d0
> #define RING_BBSTATE(base) ((base)+0x110)
> +#define RING_BB_PPGTT (1 << 5)
> +#define RING_SBBADDR(base) ((base)+0x114) /* hsw+ */
> +#define RING_SBBSTATE(base) ((base)+0x118) /* hsw+ */
> +#define RING_SBBADDR_UDW(base) ((base)+0x11c) /* gen8+ */
> #define RING_BBADDR(base) ((base)+0x140)
> #define RING_BBADDR_UDW(base) ((base)+0x168) /* gen8+ */
> +#define RING_BB_PER_CTX_PTR(base) ((base)+0x1c0) /* gen8+ */
> +#define RING_INDIRECT_CTX(base) ((base)+0x1c4) /* gen8+ */
> +#define RING_INDIRECT_CTX_OFFSET(base) ((base)+0x1c8) /* gen8+ */
> +#define RING_CTX_TIMESTAMP(base) ((base)+0x3a8) /* gen8+ */
>
> #define ERROR_GEN6 0x040a0
> #define GEN7_ERR_INT 0x44040
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> b/drivers/gpu/drm/i915/intel_lrc.c
> index 221c478..1df4028 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -2287,24 +2287,24 @@ populate_lr_context(struct intel_context *ctx, struct
> drm_i915_gem_object *ctx_o
> reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);
> reg_state[CTX_RING_BUFFER_CONTROL+1] =
> ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) |
> RING_VALID;
> - reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;
> + reg_state[CTX_BB_HEAD_U] = RING_BBADDR_UDW(ring->mmio_base);
Imagine the possibilities!
#define SET(idx, reg, val) do {
reg_state[(idx)] = (reg);
reg_state[(idx)+1] = (val);
} while(0)
#define RING_SET(idx, reg, val) SET(idx, reg(ring->mmio_base), 0)
RING_SET(CTX_BB_HEAD_L, RING_BBADDR_LDW, 0)
RING_SET(CTX_BB_HEAD_U, RING_BBADDR_UDW, 0)
...
Now if only the reg_state indicies were canonically named.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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