On Fri, Jan 22, 2016 at 01:28:45PM +0200, Gabriel Feceoru wrote: > Some Gen7/8 production parts may have the Display Pipe C fused off. > In this case, the display hardware will prevent the enable bit in > PIPE_CONF register (for Pipe C) from being set to 1. > > Fixed by adjusting pipe_count to reflect this. > > v2: Rename HSW_PIPE_C_DISABLE to IVB_PIPE_C_DISABLE as it already exists > on ivybridge (Ville) > v3: Remove unnecessary MMIO read, correct the description (Damien) > v4: Be more specific in description (Patrick) > > Signed-off-by: Gabriel Feceoru <gabriel.fece...@intel.com>
Reviewed-by: Patrik Jakobsson <patrik.jakobs...@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_dma.c | 3 +++ > drivers/gpu/drm/i915/i915_reg.h | 1 + > 2 files changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c > index d70d96f..91404aa 100644 > --- a/drivers/gpu/drm/i915/i915_dma.c > +++ b/drivers/gpu/drm/i915/i915_dma.c > @@ -816,6 +816,9 @@ static void intel_device_info_runtime_init(struct > drm_device *dev) > !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { > DRM_INFO("Display fused off, disabling\n"); > info->num_pipes = 0; > + } else if (fuse_strap & IVB_PIPE_C_DISABLE) { > + DRM_INFO("PipeC fused off\n"); > + info->num_pipes -= 1; > } > } > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 0a98889..a182739 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -5945,6 +5945,7 @@ enum skl_disp_power_wells { > #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31) > #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30) > #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29) > +#define IVB_PIPE_C_DISABLE (1 << 28) > #define ILK_HDCP_DISABLE (1 << 25) > #define ILK_eDP_A_DISABLE (1 << 24) > #define HSW_CDCLK_LIMIT (1 << 24) > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- --- Intel Sweden AB Registered Office: Knarrarnasgatan 15, 164 40 Kista, Stockholm, Sweden Registration Number: 556189-6027 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx