From: Ville Syrjälä <[email protected]>
Here's a pile of pending VLV/CHV DSI and DPLL patches I had lying around.
Most of these have been posted before. Would be nice to finally get them
in.
I've tried to rebase things to account for BXT as well, but obviously
that part is not tested. I have tested this on a BYT FFRD8 which has
a DSI panel.
Apart from the VLV/CHV specific stuff, the main thing here is moving
the DSI PLL calculations to the .compute_config() phase. Another neat
thing is hooking up the panel fitter for DSI.
Ville Syrjälä (16):
drm/i915: Throw out BUGs from DPLL/PCH functions
drm/i915: Make {vlv,chv}_{disable,update}_pll() more similar
drm/i915: Implement WaPixelRepeatModeFixForC0:chv
drm/i915: Add a local pipe variable to vlv_enable_pll()
drm/i915: assert_panel_unlocked() in chv_enable_pll()
drm/i915: Remove the "three times for luck" trick from
vlv_enable_pll()
drm/i915: Setup DPLL/DPLLMD for DSI too on VLV/CHV
drm/i915: Don't read out port_clock on CHV when DPLL is disabled
drm/i915: Change lfsr_converts[] to u16
drm/i915: Power down the DSI PLL before reconfiguring it
drm/i915: Compute DSI PLL parameters during .compute_config()
drm/i915: Fix CHV DSI PLL refclk during state readout
drm/i915: Eliminate {vlv,bxt}_configure_dsi_pll()
drm/i915: Dump pfit PGM_RATIOS as hex
drm/i915: Hook up pfit for DSI
drm/i915: Reject 'Center' scaling mode for eDP/DSI on GMCH platforms
drivers/gpu/drm/i915/i915_drv.h | 7 +
drivers/gpu/drm/i915/i915_reg.h | 4 +
drivers/gpu/drm/i915/intel_display.c | 244 +++++++++++++++++++----------------
drivers/gpu/drm/i915/intel_dp.c | 5 +
drivers/gpu/drm/i915/intel_drv.h | 5 +
drivers/gpu/drm/i915/intel_dsi.c | 120 +++++++++++++----
drivers/gpu/drm/i915/intel_dsi.h | 14 +-
drivers/gpu/drm/i915/intel_dsi_pll.c | 155 +++++++++++-----------
8 files changed, 332 insertions(+), 222 deletions(-)
--
2.4.10
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