On Fri, Apr 08, 2016 at 06:31:45PM +0300, Ander Conselvan de Oliveira wrote:
> The only difference between the DP and HDMI versions was the lane count.
> Since lane_count is now set appropriately for HDMI too, get rid of the
> duplication and move this to intel_dpio_phy.c
>
> Signed-off-by: Ander Conselvan de Oliveira
> <ander.conselvan.de.olive...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +
> drivers/gpu/drm/i915/intel_dp.c | 84 +------------------------------
> drivers/gpu/drm/i915/intel_dpio_phy.c | 93
> +++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_hdmi.c | 69 +-------------------------
> 4 files changed, 99 insertions(+), 149 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7b2f453..e1b2f48 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3511,6 +3511,8 @@ void chv_set_phy_signal_level(struct intel_encoder
> *encoder,
> void chv_data_lane_soft_reset(struct intel_encoder *encoder,
> bool reset);
> void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
> +void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
> +void chv_phy_release_cl2_override(struct intel_encoder *encoder);
>
> int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
> int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index fb0c9c5..8735738 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2851,91 +2851,11 @@ static void vlv_dp_pre_pll_enable(struct
> intel_encoder *encoder)
>
> static void chv_pre_enable_dp(struct intel_encoder *encoder)
> {
> - struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> - struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> - struct drm_device *dev = encoder->base.dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_crtc *intel_crtc =
> - to_intel_crtc(encoder->base.crtc);
> - enum dpio_channel ch = vlv_dport_to_channel(dport);
> - int pipe = intel_crtc->pipe;
> - int data, i, stagger;
> - u32 val;
> -
> - mutex_lock(&dev_priv->sb_lock);
> -
> - /* allow hardware to manage TX FIFO reset source */
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> - val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> -
> - if (intel_crtc->config->lane_count > 2) {
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> - val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> - }
> -
> - /* Program Tx lane latency optimal setting*/
> - for (i = 0; i < intel_crtc->config->lane_count; i++) {
> - /* Set the upar bit */
> - if (intel_crtc->config->lane_count == 1)
> - data = 0x0;
> - else
> - data = (i == 1) ? 0x0 : 0x1;
> - vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
> - data << DPIO_UPAR_SHIFT);
> - }
> -
> - /* Data lane stagger programming */
> - if (intel_crtc->config->port_clock > 270000)
> - stagger = 0x18;
> - else if (intel_crtc->config->port_clock > 135000)
> - stagger = 0xd;
> - else if (intel_crtc->config->port_clock > 67500)
> - stagger = 0x7;
> - else if (intel_crtc->config->port_clock > 33750)
> - stagger = 0x4;
> - else
> - stagger = 0x2;
> -
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> - val |= DPIO_TX2_STAGGER_MASK(0x1f);
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> -
> - if (intel_crtc->config->lane_count > 2) {
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> - val |= DPIO_TX2_STAGGER_MASK(0x1f);
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> - }
> -
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
> - DPIO_LANESTAGGER_STRAP(stagger) |
> - DPIO_LANESTAGGER_STRAP_OVRD |
> - DPIO_TX1_STAGGER_MASK(0x1f) |
> - DPIO_TX1_STAGGER_MULT(6) |
> - DPIO_TX2_STAGGER_MULT(0));
> -
> - if (intel_crtc->config->lane_count > 2) {
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
> - DPIO_LANESTAGGER_STRAP(stagger) |
> - DPIO_LANESTAGGER_STRAP_OVRD |
> - DPIO_TX1_STAGGER_MASK(0x1f) |
> - DPIO_TX1_STAGGER_MULT(7) |
> - DPIO_TX2_STAGGER_MULT(5));
> - }
> -
> - /* Deassert data lane reset */
> - chv_data_lane_soft_reset(encoder, false);
> -
> - mutex_unlock(&dev_priv->sb_lock);
> + chv_phy_pre_encoder_enable(encoder);
>
> intel_enable_dp(encoder);
>
> - /* Second common lane will stay alive on its own now */
These comments would be better left in the caller.
> - if (dport->release_cl2_override) {
> - chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
> - dport->release_cl2_override = false;
> - }
> + chv_phy_release_cl2_override(encoder);
> }
>
> static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c
> b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index b4ca3ff..6078e74 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -244,3 +244,96 @@ void chv_phy_pre_pll_enable(struct intel_encoder
> *encoder)
>
> mutex_unlock(&dev_priv->sb_lock);
> }
> +
> +void chv_phy_pre_encoder_enable(struct intel_encoder *encoder)
> +{
> + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> + struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> + struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_crtc *intel_crtc =
> + to_intel_crtc(encoder->base.crtc);
> + enum dpio_channel ch = vlv_dport_to_channel(dport);
> + int pipe = intel_crtc->pipe;
> + int data, i, stagger;
> + u32 val;
> +
> + mutex_lock(&dev_priv->sb_lock);
> +
> + /* allow hardware to manage TX FIFO reset source */
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> + val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> +
> + if (intel_crtc->config->lane_count > 2) {
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> + val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> + }
> +
> + /* Program Tx lane latency optimal setting*/
> + for (i = 0; i < intel_crtc->config->lane_count; i++) {
> + /* Set the upar bit */
> + if (intel_crtc->config->lane_count == 1)
> + data = 0x0;
> + else
> + data = (i == 1) ? 0x0 : 0x1;
> + vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
> + data << DPIO_UPAR_SHIFT);
> + }
> +
> + /* Data lane stagger programming */
> + if (intel_crtc->config->port_clock > 270000)
> + stagger = 0x18;
> + else if (intel_crtc->config->port_clock > 135000)
> + stagger = 0xd;
> + else if (intel_crtc->config->port_clock > 67500)
> + stagger = 0x7;
> + else if (intel_crtc->config->port_clock > 33750)
> + stagger = 0x4;
> + else
> + stagger = 0x2;
> +
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> + val |= DPIO_TX2_STAGGER_MASK(0x1f);
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> +
> + if (intel_crtc->config->lane_count > 2) {
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> + val |= DPIO_TX2_STAGGER_MASK(0x1f);
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> + }
> +
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
> + DPIO_LANESTAGGER_STRAP(stagger) |
> + DPIO_LANESTAGGER_STRAP_OVRD |
> + DPIO_TX1_STAGGER_MASK(0x1f) |
> + DPIO_TX1_STAGGER_MULT(6) |
> + DPIO_TX2_STAGGER_MULT(0));
> +
> + if (intel_crtc->config->lane_count > 2) {
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
> + DPIO_LANESTAGGER_STRAP(stagger) |
> + DPIO_LANESTAGGER_STRAP_OVRD |
> + DPIO_TX1_STAGGER_MASK(0x1f) |
> + DPIO_TX1_STAGGER_MULT(7) |
> + DPIO_TX2_STAGGER_MULT(5));
> + }
> +
> + /* Deassert data lane reset */
> + chv_data_lane_soft_reset(encoder, false);
> +
> + mutex_unlock(&dev_priv->sb_lock);
> +}
> +
> +void chv_phy_release_cl2_override(struct intel_encoder *encoder)
> +{
> + struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> + /* Second common lane will stay alive on its own now */
> + if (dport->release_cl2_override) {
> + chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
> + dport->release_cl2_override = false;
> + }
> +}
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index 4501906..1eb6667 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1734,69 +1734,8 @@ static void chv_hdmi_pre_enable(struct intel_encoder
> *encoder)
> struct intel_crtc *intel_crtc =
> to_intel_crtc(encoder->base.crtc);
> const struct drm_display_mode *adjusted_mode =
> &intel_crtc->config->base.adjusted_mode;
> - enum dpio_channel ch = vlv_dport_to_channel(dport);
> - int pipe = intel_crtc->pipe;
> - int data, i, stagger;
> - u32 val;
> -
> - mutex_lock(&dev_priv->sb_lock);
> -
> - /* allow hardware to manage TX FIFO reset source */
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> - val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> -
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> - val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> -
> - /* Program Tx latency optimal setting */
> - for (i = 0; i < 4; i++) {
> - /* Set the upar bit */
> - data = (i == 1) ? 0x0 : 0x1;
> - vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
> - data << DPIO_UPAR_SHIFT);
> - }
> -
> - /* Data lane stagger programming */
> - if (intel_crtc->config->port_clock > 270000)
> - stagger = 0x18;
> - else if (intel_crtc->config->port_clock > 135000)
> - stagger = 0xd;
> - else if (intel_crtc->config->port_clock > 67500)
> - stagger = 0x7;
> - else if (intel_crtc->config->port_clock > 33750)
> - stagger = 0x4;
> - else
> - stagger = 0x2;
> -
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> - val |= DPIO_TX2_STAGGER_MASK(0x1f);
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
> -
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
> - val |= DPIO_TX2_STAGGER_MASK(0x1f);
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
> -
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
> - DPIO_LANESTAGGER_STRAP(stagger) |
> - DPIO_LANESTAGGER_STRAP_OVRD |
> - DPIO_TX1_STAGGER_MASK(0x1f) |
> - DPIO_TX1_STAGGER_MULT(6) |
> - DPIO_TX2_STAGGER_MULT(0));
> -
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
> - DPIO_LANESTAGGER_STRAP(stagger) |
> - DPIO_LANESTAGGER_STRAP_OVRD |
> - DPIO_TX1_STAGGER_MASK(0x1f) |
> - DPIO_TX1_STAGGER_MULT(7) |
> - DPIO_TX2_STAGGER_MULT(5));
> -
> - /* Deassert data lane reset */
> - chv_data_lane_soft_reset(encoder, false);
> -
> - mutex_unlock(&dev_priv->sb_lock);
>
> + chv_phy_pre_encoder_enable(encoder);
> chv_set_phy_signal_level(encoder, 128, 102, false);
>
> intel_hdmi->set_infoframes(&encoder->base,
> @@ -1807,11 +1746,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder
> *encoder)
>
> vlv_wait_port_ready(dev_priv, dport, 0x0);
>
> - /* Second common lane will stay alive on its own now */
> - if (dport->release_cl2_override) {
> - chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
> - dport->release_cl2_override = false;
> - }
> + chv_phy_release_cl2_override(encoder);
> }
>
> static void intel_hdmi_destroy(struct drm_connector *connector)
> --
> 2.4.11
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
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