If we can't find any valid level 0 watermark values for the requested
atomic transaction, reject the configuration before we try to start
programming the hardware.
Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankho...@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 59d4574..96ffd54 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3309,7 +3309,17 @@ static int skl_compute_plane_wm(const struct
drm_i915_private *dev_priv,
if (res_blocks >= ddb_allocation || res_lines > 31) {
*enabled = false;
- return 0;
+
+ /*
+ * If there are no valid level 0 watermarks, then we can't
+ * support this display configuration.
+ */
+ if (level) {
+ return 0;
+ } else {
+ DRM_DEBUG_KMS("Requested display configuration exceeds
system watermark limitations\n");
+ return -EINVAL;
+ }
}
*out_blocks = res_blocks;
--
2.1.4
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