On Tue, Aug 02, 2016 at 02:16:02PM +0300, Imre Deak wrote:
> On ti, 2016-08-02 at 14:07 +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrj...@linux.intel.com>
> >
> > Remove the CHV early bail out from intel_cleanup_gt_powersave() so that
> > we'll clean up the extra RPM reference held due to i915.enable_rc6=0.
> >
> > Cc: Imre Deak <imre.d...@intel.com>
> > Fixes: b268c699aca5 ("drm/i915: refactor RPM disabling due to RC6 being
> > disabled")
> > Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
>
> Thanks for catching it:
> Reviewed-by: Imre Deak <imre.d...@intel.com>
Pushed to dinq. Thanks for the review.
>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 4 +---
> > 1 file changed, 1 insertion(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 1ac32428d4db..125faac2fb5d 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -6533,9 +6533,7 @@ void intel_init_gt_powersave(struct drm_i915_private
> > *dev_priv)
> >
> > void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
> > {
> > - if (IS_CHERRYVIEW(dev_priv))
> > - return;
> > - else if (IS_VALLEYVIEW(dev_priv))
> > + if (IS_VALLEYVIEW(dev_priv))
> > valleyview_cleanup_gt_powersave(dev_priv);
> >
> > if (!i915.enable_rc6)
--
Ville Syrjälä
Intel OTC
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