From: Tom O'Rourke <Tom.O'rou...@intel.com>
Add host2guc SLPC reset event and send reset event
during enable.
v2: extract host2guc_slpc to handle slpc status code
coding style changes (Paulo)
v5: Removed WARN_ON for checking msb of gtt address of
shared gem obj. (ChrisW)
host2guc_action to i915_guc_action change.(Sagar)
Updating SLPC enabled status. (Sagar)
Signed-off-by: Tom O'Rourke <Tom.O'rou...@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
drivers/gpu/drm/i915/intel_slpc.c | 29 +++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_slpc.h | 14 ++++++++++++++
2 files changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_slpc.c
b/drivers/gpu/drm/i915/intel_slpc.c
index ba5b23a..161cd13 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -26,6 +26,32 @@
#include "i915_drv.h"
#include "intel_guc.h"
+static void host2guc_slpc(struct drm_i915_private *dev_priv, u32 *data, u32
len)
+{
+ int ret = i915_guc_action(&dev_priv->guc, data, len);
+
+ if (!ret) {
+ ret = I915_READ(SOFT_SCRATCH(1));
+ ret &= SLPC_EVENT_STATUS_MASK;
+ }
+
+ if (ret)
+ DRM_ERROR("event 0x%x status %d\n", (data[1] >> 8), ret);
+}
+
+static void host2guc_slpc_reset(struct drm_i915_private *dev_priv)
+{
+ u32 data[4];
+ u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma);
+
+ data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+ data[1] = SLPC_EVENT(SLPC_EVENT_RESET, 2);
+ data[2] = shared_data_gtt_offset;
+ data[3] = 0;
+
+ host2guc_slpc(dev_priv, data, 4);
+}
+
static u8 slpc_get_platform_sku(struct drm_device *dev)
{
enum slpc_platform_sku platform_sku;
@@ -133,6 +159,9 @@ void intel_slpc_disable(struct drm_i915_private *dev_priv)
void intel_slpc_enable(struct drm_i915_private *dev_priv)
{
+ host2guc_slpc_reset(dev_priv);
+ dev_priv->guc.slpc.enabled = true;
+
return;
}
diff --git a/drivers/gpu/drm/i915/intel_slpc.h
b/drivers/gpu/drm/i915/intel_slpc.h
index e951289..031e36b 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -28,6 +28,20 @@
#define SLPC_MINOR_VER 4
#define SLPC_VERSION ((2015 << 16) | (SLPC_MAJOR_VER << 8) | (SLPC_MINOR_VER))
+enum slpc_event_id {
+ SLPC_EVENT_RESET = 0,
+ SLPC_EVENT_SHUTDOWN = 1,
+ SLPC_EVENT_PLATFORM_INFO_CHANGE = 2,
+ SLPC_EVENT_DISPLAY_MODE_CHANGE = 3,
+ SLPC_EVENT_FLIP_COMPLETE = 4,
+ SLPC_EVENT_QUERY_TASK_STATE = 5,
+ SLPC_EVENT_PARAMETER_SET = 6,
+ SLPC_EVENT_PARAMETER_UNSET = 7,
+};
+
+#define SLPC_EVENT(id, argc) ((u32) (id) << 8 | (argc))
+#define SLPC_EVENT_STATUS_MASK 0xFF
+
enum slpc_global_state {
SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
SLPC_GLOBAL_STATE_INITIALIZING = 1,
--
1.9.1
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