It is possible that from Skylake onwards the initial plane is tiled in
some other format than X. Copy across this information to the object
when such formats are fence-able.
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_display.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index e363a68d97ed..187e499107af 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2700,8 +2700,15 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
return false;
}
- if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
- obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
+ if (fb->modifier[0]) {
+ obj->tiling_and_stride = fb->pitches[0];
+ if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
+ obj->tiling_and_stride |= I915_TILING_X;
+ else if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED)
+ obj->tiling_and_stride |= I915_TILING_Y;
+ else
+ obj->tiling_and_stride = 0; /* unfenced tiling mode */
+ }
mode_cmd.pixel_format = fb->pixel_format;
mode_cmd.width = fb->width;
--
2.9.3
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