This series implements new DDB allocation algorithm to solve the cases, where we have sufficient DDB available to enable multiple planes, But due to the current algorithm not dividing it properly among planes, we end-up failing the flip. It also takes care of enabling same watermark level for each plane, for efficient power saving. This series also implements Transition Watermarks and Gen-9 related arbitrated display bandwidth Workarounds.
There are two steps in current WM programming. 1. Calculate minimum number of blocks required for a WM level to be enabled. For 1440x2560 panel we need 41 blocks as minimum number of blocks to enable WM0. This is the step which doesn't use vertical size. It only depends on Pipe drain rate and plane horizontal size as per the current Bspec algorithm. So all the plane below have minimum number of blocks required to enable WM0 as 41 Plane 1 - 1440x2560 - Min blocks to enable WM0 = 41 Plane 2 - 1440x2560 - Min blocks to enable WM0 = 41 Plane 3 - 1440x48 - Min blocks to enable WM0 = 41 Plane 4 - 1440x96 - Min blocks to enable WM0 = 41 2. Number of blocks allotted by the driver Driver allocates 12 for Plane 3 & 16 for plane 4 Total Dbuf Available = 508 Dbuf Available after 32 blocks for cursor = 508 - (32) = 476 allocate minimum blocks for each plane 8 * 4 = 32 remaining blocks = 476 - 32 = 444 Relative Data Rate for Planes Plane 1 = 1440 * 2560 * 3 = 11059200 Plane 2 = 1440 * 2560 * 3 = 11059200 Plane 3 = 1440 * 48 * 3 = 207360 Plane 4 = 1440 * 96 * 3 = 414720 Total Relative BW = 22740480 - Allocate Buffer buffer allocation = (Plane relative data rate / total data rate) * total remaming DDB + minimum plane DDB Plane 1 buffer allocation = (11059200 / 22740480) * 444 + 8 = 223 Plane 2 buffer allocation = (11059200 / 22740480) * 444 + 8 = 223 Plane 3 buffer allocation = (207360 / 22740480) * 444 + 8 = 12 Plane 4 buffer allocation = (414720 / 22740480) * 444 + 8 = 16 In this case it forced driver to disable Plane 3 & 4. Driver need to use more efficient way to allocate buffer that is optimum for power. New Algorithm suggested by HW team is: 1. Calculate minimum buffer allocations for each plane and for each watermark level 2. Add minimum buffer allocations required for enabling WM7 for all the planes Level 0 = 41 + 41 + 41 + 41 = 164 Level 1 = 42 + 42 + 42 + 42 = 168 Level 2 = 42 + 42 + 42 + 42 = 168 Level 3 = 94 + 94 + 94 + 94 = 376 Level 4 = 94 + 94 + 94 + 94 = 376 Level 5 = 94 + 94 + 94 + 94 = 376 Level 6 = 94 + 94 + 94 + 94 = 376 Level 7 = 94 + 94 + 94 + 94 = 376 3. Check to see how many buffer allocation are left and enable the best case. In this case since we have 476 blocks we can enable WM0-7 on all 4 planes. Let's say if we have only 200 block available then the best cases allocation is to enable Level2 which requires 168 blocks Kumar, Mahesh (7): drm/i915/hsw+: set intel_crtc active once pipe is active drm/i915/skl+: use linetime latency instead of ddb size drm/i915/skl: pass pipe_wm in skl_compute_(wm_level/plane_wm) functions drm/i915/skl: New ddb allocation algorithm drm/i915: Decode system memory bandwidth FOR_UPSTREAM [VPG]: drm/i915/skl+: Implement Transition WM drm/i915/gen9: WM memory bandwidth related workaround drivers/gpu/drm/i915/i915_drv.c | 96 +++++++++ drivers/gpu/drm/i915/i915_drv.h | 27 +++ drivers/gpu/drm/i915/i915_reg.h | 25 +++ drivers/gpu/drm/i915/intel_display.c | 4 +- drivers/gpu/drm/i915/intel_drv.h | 11 ++ drivers/gpu/drm/i915/intel_pm.c | 366 +++++++++++++++++++++++++++-------- 6 files changed, 447 insertions(+), 82 deletions(-) -- 2.8.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx