The latest Intel platform used two clocks for 1588 time synchronization dependent on the HW strap: 24 MHz and 38.4 MHz. The maximum possible frequency adjustment, in parts per billion, calculated as follows: max ppb = ((MAX_INCVAL – BASE_INCVAL)*1billion) / BASE_INCVAL. Where MAX_INCVAL is TIMINCA resolution (2^24 -1) and BASE_INCVAL is depends on the clock. For 24 MHz the max ppb value should be 600,000,000 and for the 38.4MHz the max ppb value is 230,000,000.
Reported-by: Trey Harrison <[email protected]> Fixes: d89777bf0e42 ("e1000e: add support for IEEE-1588 PTP") Reviewed-by: Jacob Keller <[email protected]> Signed-off-by: Sasha Neftin <[email protected]> --- drivers/net/ethernet/intel/e1000e/ptp.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/intel/e1000e/ptp.c b/drivers/net/ethernet/intel/e1000e/ptp.c index 02d871bc112a..792dfe602ca0 100644 --- a/drivers/net/ethernet/intel/e1000e/ptp.c +++ b/drivers/net/ethernet/intel/e1000e/ptp.c @@ -283,17 +283,24 @@ void e1000e_ptp_init(struct e1000_adapter *adapter) case e1000_pch_lpt: case e1000_pch_spt: case e1000_pch_cnp: + if (hw->mac.type < e1000_pch_lpt || + (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) { + adapter->ptp_clock_info.max_adj = 24000000 - 1; + break; + } + fallthrough; case e1000_pch_tgp: case e1000_pch_adp: case e1000_pch_mtp: case e1000_pch_lnp: case e1000_pch_ptp: case e1000_pch_nvp: - if ((hw->mac.type < e1000_pch_lpt) || - (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) { - adapter->ptp_clock_info.max_adj = 24000000 - 1; - break; - } + if (hw->mac.type < e1000_pch_lpt || + (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) + adapter->ptp_clock_info.max_adj = 600000000 - 1; + else + adapter->ptp_clock_info.max_adj = 230000000 - 1; + break; fallthrough; case e1000_82574: case e1000_82583: -- 2.34.1 _______________________________________________ Intel-wired-lan mailing list [email protected] https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
