On 9/30/2024 5:08 AM, Karol Kolacinski wrote:
Quad registers are read/written incorrectly. E825 devices always use
quad 0 address and differentiate between the PHYs by changing SBQ
destination device (phy_0 or phy_0_peer).
Add helpers for reading/writing PTP registers shared per quad and use
correct quad address and SBQ destination device based on port.
Rename rmn_0 to phy_0 and remove rmn_1 and rmn_2 as E82X HW does not
support it. Rename eth56g_phy_1 to phy_0_peer.
Fixes: 7cab44f1c35f ("ice: Introduce ETH56G PHY model for E825C products")
Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalew...@intel.com>
Signed-off-by: Karol Kolacinski <karol.kolacin...@intel.com>
There's a bunch of kdoc issues being reported.
Mostly missing 'Return:' but struct ice_phy_reg_info_eth56g also needs
its kdoc updated.
...
+/**
+ * ice_ptp_get_dest_dev_e825 - get destination PHY for given port number
+ * @hw: pointer to the HW struct
+ * @port: destination port
+ */
+static enum ice_sbq_msg_dev ice_ptp_get_dest_dev_e825(struct ice_hw *hw,
+ u8 port)
+{
+ /* On a single complex E825C, PHY 0 is always destination device phy_0
+ * and PHY 1 is phy_0_peer.
+ */
+ if (port / hw->ptp.ports_per_phy)
+ return phy_0_peer;
+ else
+ return phy_0;
smatch reports:
drivers/net/ethernet/intel/ice/ice_ptp_hw.c:920
ice_ptp_get_dest_dev_e825() warn: replace divide condition 'port /
hw->ptp.ports_per_phy' with 'port >= hw->ptp.ports_per_phy'
Oddly on a different patch, but it was introduced here.
Thanks,
Tony
