> -----Original Message----- > From: Intel-wired-lan <[email protected]> On Behalf Of Kurt > Kanzenbach > Sent: 17 February 2025 17:01 > To: Nguyen, Anthony L <[email protected]>; Kitszel, Przemyslaw > <[email protected]> > Cc: Andrew Lunn <[email protected]>; David S. Miller > <[email protected]>; Eric Dumazet <[email protected]>; Jakub Kicinski > <[email protected]>; Paolo Abeni <[email protected]>; Sebastian Andrzej Siewior > <[email protected]>; Damato, Joe <[email protected]>; Gerhard Engleder > <[email protected]>; [email protected]; > [email protected]; Kurt Kanzenbach <[email protected]> > Subject: [Intel-wired-lan] [PATCH iwl-next v2 2/4] igb: Link queues to NAPI > instances > > Link queues to NAPI instances via netdev-genl API. This is required to use > XDP/ZC busy polling. See commit 5ef44b3cb43b ("xsk: Bring back busy polling support") for details. > > This also allows users to query the info with netlink: > > |$ ./tools/net/ynl/pyynl/cli.py --spec > Documentation/netlink/specs/netdev.yaml \ > | --dump queue-get --json='{"ifindex": 2}' > |[{'id': 0, 'ifindex': 2, 'napi-id': 8201, 'type': 'rx'}, > | {'id': 1, 'ifindex': 2, 'napi-id': 8202, 'type': 'rx'}, > | {'id': 2, 'ifindex': 2, 'napi-id': 8203, 'type': 'rx'}, > | {'id': 3, 'ifindex': 2, 'napi-id': 8204, 'type': 'rx'}, > | {'id': 0, 'ifindex': 2, 'napi-id': 8201, 'type': 'tx'}, > | {'id': 1, 'ifindex': 2, 'napi-id': 8202, 'type': 'tx'}, > | {'id': 2, 'ifindex': 2, 'napi-id': 8203, 'type': 'tx'}, > | {'id': 3, 'ifindex': 2, 'napi-id': 8204, 'type': 'tx'}] > > Add rtnl locking to PCI error handlers, because netif_queue_set_napi() > requires the lock held. > > While at __igb_open() use RCT coding style. > > Signed-off-by: Kurt Kanzenbach <[email protected]> > --- > drivers/net/ethernet/intel/igb/igb.h | 2 ++ > drivers/net/ethernet/intel/igb/igb_main.c | 43 > +++++++++++++++++++++++++++---- drivers/net/ethernet/intel/igb/igb_xsk.c | > 2 ++ > 3 files changed, 42 insertions(+), 5 deletions(-) >
Tested-by: Rinitha S <[email protected]> (A Contingent worker at Intel)
