> -----Original Message----- > From: Loktionov, Aleksandr <[email protected]> > Sent: Wednesday, August 13, 2025 12:10 PM > To: Nitka, Grzegorz <[email protected]>; intel-wired- > [email protected] > Cc: [email protected]; [email protected]; Kubalewski, > Arkadiusz <[email protected]>; Korba, Przemyslaw > <[email protected]>; Nguyen, Anthony L > <[email protected]>; Olech, Milena <[email protected]> > Subject: RE: [Intel-wired-lan] [PATCH v9 iwl-next] ice: add recovery clock and > clock 1588 control for E825c > > > > > -----Original Message----- > > From: Intel-wired-lan <[email protected]> On Behalf > > Of Grzegorz Nitka > > Sent: Tuesday, August 12, 2025 10:20 PM > > To: [email protected] > > Cc: [email protected]; [email protected]; Kubalewski, > > Arkadiusz <[email protected]>; Korba, Przemyslaw > > <[email protected]>; Nguyen, Anthony L > > <[email protected]>; Olech, Milena <[email protected]> > > Subject: [Intel-wired-lan] [PATCH v9 iwl-next] ice: add recovery > > clock and clock 1588 control for E825c > > > > From: Przemyslaw Korba <[email protected]> > > > > Add control for E825 input pins: phy clock recovery and clock 1588. > > E825 does not provide control over platform level DPLL but it > > provides control over PHY clock recovery, and PTP/timestamp driven > > inputs for platform level DPLL [1]. > > > > Introduce a software controlled layer of abstraction to: > > - create a DPLL of type EEC for E825c, > > - create recovered clock pin for each PF, and control them through > > writing to registers, > > - create pin to control clock 1588 for PF0, and control it through > > writing to registers. > > > > ... > > > + > > +#define ICE_CGU_R10 0x28 > > +#define ICE_CGU_R10_SYNCE_CLKO_SEL GENMASK(8, 5) > > +#define ICE_CGU_R10_SYNCE_CLKODIV_M1 > GENMASK(13, 9) > > +#define ICE_CGU_R10_SYNCE_CLKODIV_LOAD BIT(14) > > +#define ICE_CGU_R10_SYNCE_DCK_RST BIT(15) > > +#define ICE_CGU_R10_SYNCE_ETHCLKO_SEL > GENMASK(18, 16) > > +#define ICE_CGU_R10_SYNCE_ETHDIV_M1 GENMASK(23, 19) > > +#define ICE_CGU_R10_SYNCE_ETHDIV_LOAD BIT(24) > > +#define ICE_CGU_R10_SYNCE_DCK2_RST BIT(25) > > +#define ICE_CGU_R10_SYNCE_S_REF_CLK GENMASK(31, 27) > > + > > +#define ICE_CGU_R11 0x2C > > +#define ICE_CGU_R11_SYNCE_S_BYP_CLK GENMASK(6, 1) > > + > > +#define ICE_CGU_BYPASS_MUX_OFFSET_E825C 3 > > + > > +#define SET_PIN_STATE(_pin, _id, _condition) \ > > + ((_pin)->state[_id] = (_condition) ? DPLL_PIN_STATE_CONNECTED > > : \ > > + DPLL_PIN_STATE_DISCONNECTED) > Can you consider implement it as inline function instead of macro? > > Alex
Apologize for late response (summer break time). To be changed in v10.
