[Intel-wired-lan] [PATCH net-next v5 4/5] net/mlx5e: Report RS-FEC histogram statistics via ethtool

[Vadim Fedorenko]

From: Carolina Jubran <cjub...@nvidia.com>

Add support for reporting RS-FEC histogram counters by reading them
from the RS_FEC_HISTOGRAM_GROUP in the PPCNT register.

Co-developed-by: Yael Chemla <yche...@nvidia.com>
Signed-off-by: Yael Chemla <yche...@nvidia.com>
Signed-off-by: Carolina Jubran <cjub...@nvidia.com>
Reviewed-by: Dragos Tatulea <dtatu...@nvidia.com>
Reviewed-by: Yael Chemla <yche...@nvidia.com>
---
 .../ethernet/mellanox/mlx5/core/en_stats.c    | 34 ++++++++++++++++++-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c 
b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c
index e6613672b8f5..ffc4f9b4f284 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c
@@ -1552,15 +1552,47 @@ fec_rs_histogram_fill_ranges(struct mlx5e_priv *priv, 
int mode,
        return num_of_bins;
 }
 
+static void fec_rs_histogram_fill_stats(struct mlx5e_priv *priv,
+                                       u8 num_of_bins,
+                                       struct ethtool_fec_hist *hist)
+{
+       struct mlx5_core_dev *mdev = priv->mdev;
+       u32 out[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
+       u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
+       int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
+       void *rs_histogram_cntrs;
+
+       MLX5_SET(ppcnt_reg, in, local_port, 1);
+       MLX5_SET(ppcnt_reg, in, grp, MLX5_RS_FEC_HISTOGRAM_GROUP);
+       if (mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0))
+               return;
+
+       rs_histogram_cntrs = MLX5_ADDR_OF(ppcnt_reg, out,
+                                         counter_set.rs_histogram_cntrs);
+       /* Guaranteed that num_of_bins is less than MLX5E_FEC_RS_HIST_MAX
+        * by fec_rs_histogram_fill_ranges().
+        */
+       for (int i = 0; i < num_of_bins; i++)
+               hist->values[i].sum = MLX5_GET64(rs_histogram_cntrs,
+                                                rs_histogram_cntrs,
+                                                hist[i]);
+}
+
 static void fec_set_histograms_stats(struct mlx5e_priv *priv, int mode,
                                     struct ethtool_fec_hist *hist)
 {
+       u8 num_of_bins;
+
        switch (mode) {
        case MLX5E_FEC_RS_528_514:
        case MLX5E_FEC_RS_544_514:
        case MLX5E_FEC_LLRS_272_257_1:
        case MLX5E_FEC_RS_544_514_INTERLEAVED_QUAD:
-               fec_rs_histogram_fill_ranges(priv, mode, &hist->ranges);
+               num_of_bins =
+                       fec_rs_histogram_fill_ranges(priv, mode, &hist->ranges);
+               if (num_of_bins)
+                       return fec_rs_histogram_fill_stats(priv, num_of_bins,
+                                                          hist);
                break;
        default:
                return;
-- 
2.47.3