> -----Original Message-----
> From: Intel-wired-lan <[email protected]> On Behalf
> Of Ivan Vecera
> Sent: Tuesday, February 10, 2026 11:43 AM
> To: [email protected]
> Cc: Kitszel, Przemyslaw <[email protected]>; open list
> <[email protected]>; Kubalewski, Arkadiusz
> <[email protected]>; Loktionov, Aleksandr
> <[email protected]>; Andrew Lunn <[email protected]>;
> Eric Dumazet <[email protected]>; Nguyen, Anthony L
> <[email protected]>; moderated list:INTEL ETHERNET DRIVERS
> <[email protected]>; Jakub Kicinski <[email protected]>;
> Paolo Abeni <[email protected]>; David S. Miller <[email protected]>
> Subject: [Intel-wired-lan] [PATCH net-next] ice: dpll: fix rclk pin
> state get and misplaced header macros
>
> Fix two issues introduced in commit ad1df4f2d591 ("ice: dpll: Support
> E825-C SyncE and dynamic pin discovery"):
>
> * The refactoring of ice_dpll_rclk_state_on_pin_get() to use
> ice_dpll_pin_get_parent_idx() omitted the base_rclk_idx adjustment
> that was correctly added in the ice_dpll_rclk_state_on_pin_set()
> path.
> This breaks E810 devices where base_rclk_idx is non-zero, causing
> the wrong hardware index to be used for pin state lookup and
> incorrect
> recovered clock state to be reported via the DPLL subsystem. E825C
> is
> unaffected as its base_rclk_idx is 0.
>
> * Add bounds check against ICE_DPLL_RCLK_NUM_MAX on hw_idx after the
> base_rclk_idx subtraction in both
> ice_dpll_rclk_state_on_pin_{get,set}()
> to prevent out-of-bounds access on the pin state array.
>
> * The CGU register definitions (ICE_CGU_R10, ICE_CGU_R11 and related
> field
> masks) were placed after the #endif of the _ICE_DPLL_H_ include
> guard,
> leaving them unprotected. Move them inside the guard.
>
> Fixes: ad1df4f2d591 ("ice: dpll: Support E825-C SyncE and dynamic pin
> discovery")
> Signed-off-by: Ivan Vecera <[email protected]>
> ---
> drivers/net/ethernet/intel/ice/ice_dpll.c | 5 ++++
> drivers/net/ethernet/intel/ice/ice_dpll.h | 32 +++++++++++------------
> 2 files changed, 21 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c
> b/drivers/net/ethernet/intel/ice/ice_dpll.c
> index baf02512d041a..73a4e28ed75fc 100644
> --- a/drivers/net/ethernet/intel/ice/ice_dpll.c
> +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c
> @@ -2440,6 +2440,8 @@ ice_dpll_rclk_state_on_pin_set(const struct
> dpll_pin *pin, void *pin_priv,
> if (hw_idx < 0)
> goto unlock;
> hw_idx -= pf->dplls.base_rclk_idx;
> + if (hw_idx >= ICE_DPLL_RCLK_NUM_MAX)
> + goto unlock;
>
> if ((enable && p->state[hw_idx] == DPLL_PIN_STATE_CONNECTED) ||
> (!enable && p->state[hw_idx] ==
> DPLL_PIN_STATE_DISCONNECTED)) { @@ -2503,6 +2505,9 @@
> ice_dpll_rclk_state_on_pin_get(const struct dpll_pin *pin, void
> *pin_priv,
> hw_idx = ice_dpll_pin_get_parent_idx(p, parent_pin);
> if (hw_idx < 0)
> goto unlock;
> + hw_idx -= pf->dplls.base_rclk_idx;
> + if (hw_idx >= ICE_DPLL_RCLK_NUM_MAX)
> + goto unlock;
>
> ret = ice_dpll_pin_state_update(pf, p,
> ICE_DPLL_PIN_TYPE_RCLK_INPUT,
> extack);
> diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.h
> b/drivers/net/ethernet/intel/ice/ice_dpll.h
> index ae42cdea0ee14..8678575359b92 100644
> --- a/drivers/net/ethernet/intel/ice/ice_dpll.h
> +++ b/drivers/net/ethernet/intel/ice/ice_dpll.h
> @@ -8,6 +8,22 @@
>
> #define ICE_DPLL_RCLK_NUM_MAX 4
>
> +#define ICE_CGU_R10 0x28
> +#define ICE_CGU_R10_SYNCE_CLKO_SEL GENMASK(8, 5)
> +#define ICE_CGU_R10_SYNCE_CLKODIV_M1 GENMASK(13, 9)
> +#define ICE_CGU_R10_SYNCE_CLKODIV_LOAD BIT(14)
> +#define ICE_CGU_R10_SYNCE_DCK_RST BIT(15)
> +#define ICE_CGU_R10_SYNCE_ETHCLKO_SEL GENMASK(18, 16)
> +#define ICE_CGU_R10_SYNCE_ETHDIV_M1 GENMASK(23, 19)
> +#define ICE_CGU_R10_SYNCE_ETHDIV_LOAD BIT(24)
> +#define ICE_CGU_R10_SYNCE_DCK2_RST BIT(25)
> +#define ICE_CGU_R10_SYNCE_S_REF_CLK GENMASK(31, 27)
> +
> +#define ICE_CGU_R11 0x2C
> +#define ICE_CGU_R11_SYNCE_S_BYP_CLK GENMASK(6, 1)
> +
> +#define ICE_CGU_BYPASS_MUX_OFFSET_E825C 3
> +
> /**
> * enum ice_dpll_pin_sw - enumerate ice software pin indices:
> * @ICE_DPLL_PIN_SW_1_IDX: index of first SW pin @@ -157,19 +173,3 @@
> static inline void ice_dpll_deinit(struct ice_pf *pf) { } #endif
>
> #endif
> -
> -#define ICE_CGU_R10 0x28
> -#define ICE_CGU_R10_SYNCE_CLKO_SEL GENMASK(8, 5)
> -#define ICE_CGU_R10_SYNCE_CLKODIV_M1 GENMASK(13, 9)
> -#define ICE_CGU_R10_SYNCE_CLKODIV_LOAD BIT(14)
> -#define ICE_CGU_R10_SYNCE_DCK_RST BIT(15)
> -#define ICE_CGU_R10_SYNCE_ETHCLKO_SEL GENMASK(18, 16)
> -#define ICE_CGU_R10_SYNCE_ETHDIV_M1 GENMASK(23, 19)
> -#define ICE_CGU_R10_SYNCE_ETHDIV_LOAD BIT(24)
> -#define ICE_CGU_R10_SYNCE_DCK2_RST BIT(25)
> -#define ICE_CGU_R10_SYNCE_S_REF_CLK GENMASK(31, 27)
> -
> -#define ICE_CGU_R11 0x2C
> -#define ICE_CGU_R11_SYNCE_S_BYP_CLK GENMASK(6, 1)
> -
> -#define ICE_CGU_BYPASS_MUX_OFFSET_E825C 3
> --
> 2.52.0
Reviewed-by: Aleksandr Loktionov <[email protected]>
