[Intel-wired-lan] [PATCH iwl-net] ice: fix missing dpll notification for SW pins

[Petr Oros]

ice_dpll_notify_changes() sends dpll_pin_change_ntf() only for the
direct CGU input pin stored in d->active_input. Software-controlled
pins (SMA/U.FL) are separate dpll_pin objects that wrap a backing CGU
input, but they never receive a change notification. As a result,
userspace consumers such as synce4l that monitor SMA pins via dpll
netlink never learn when the pin state transitions (e.g. from
SELECTABLE to CONNECTED), even though 'dpll pin show' reports the
correct state on demand.

When the active input changes, also send dpll_pin_change_ntf() for any
registered SMA/U.FL input pin whose backing CGU input matches the old
or new active input.

Fixes: 2dd5d03c77e2 ("ice: redesign dpll sma/u.fl pins control")
Signed-off-by: Petr Oros <po...@redhat.com>
---
 drivers/net/ethernet/intel/ice/ice_dpll.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c 
b/drivers/net/ethernet/intel/ice/ice_dpll.c
index c2ad39bfe177db..6f855fe4c78d62 100644
--- a/drivers/net/ethernet/intel/ice/ice_dpll.c
+++ b/drivers/net/ethernet/intel/ice/ice_dpll.c
@@ -2470,13 +2470,17 @@ static u64 ice_generate_clock_id(struct ice_pf *pf)
  */
 static void ice_dpll_notify_changes(struct ice_dpll *d)
 {
+       struct ice_dplls *dplls = &d->pf->dplls;
        bool pin_notified = false;
+       int i;
 
        if (d->prev_dpll_state != d->dpll_state) {
                d->prev_dpll_state = d->dpll_state;
                dpll_device_change_ntf(d->dpll);
        }
        if (d->prev_input != d->active_input) {
+               struct dpll_pin *old = d->prev_input;
+
                if (d->prev_input)
                        dpll_pin_change_ntf(d->prev_input);
                d->prev_input = d->active_input;
@@ -2484,6 +2488,20 @@ static void ice_dpll_notify_changes(struct ice_dpll *d)
                        dpll_pin_change_ntf(d->active_input);
                        pin_notified = true;
                }
+               for (i = 0; i < ICE_DPLL_PIN_SW_NUM; i++) {
+                       if (dplls->sma[i].pin &&
+                           dplls->sma[i].direction ==
+                           DPLL_PIN_DIRECTION_INPUT &&
+                           (dplls->sma[i].input->pin == d->active_input ||
+                            dplls->sma[i].input->pin == old))
+                               dpll_pin_change_ntf(dplls->sma[i].pin);
+                       if (dplls->ufl[i].pin &&
+                           dplls->ufl[i].direction ==
+                           DPLL_PIN_DIRECTION_INPUT &&
+                           (dplls->ufl[i].input->pin == d->active_input ||
+                            dplls->ufl[i].input->pin == old))
+                               dpll_pin_change_ntf(dplls->ufl[i].pin);
+               }
        }
        if (d->prev_phase_offset != d->phase_offset) {
                d->prev_phase_offset = d->phase_offset;
-- 
2.52.0