On Thu, 4 Jun 2026 20:05:54 +0000 Nitka, Grzegorz wrote: > > On Fri, 29 May 2026 16:26:20 +0200 Grzegorz Nitka wrote: > > > NOTE: This series is intentionally submitted on net-next (not > > > intel-wired-lan) as early feedback of DPLL subsystem changes is > > > welcomed. In the past possible approaches were discussed in [1]. > > > > I dug into 3 of the issues reported by Claude here and I think all > > are really preexisting. But I don't see why we wouldn't fix those > > first, and have a clean AI scan. Please send the fixes ASAP if you > > have them, if they are trivial they may make it for tomorrow's PR. > > Thanks for your feedback. > I'm not sure if I can identify exact 3 issues you mentioned above. > I see couple pre-existing issues reported in > https://sashiko.dev/#/patchset/20260529142628.1678955-1-grzegorz.nitka%40intel.com > - 3 issues reported in [PATCH v12 net-next 3/8] dpll: extend pin notifier > with notification source ID > - 2 issues reported in [PATCH v12 net-next 5/8] ice: introduce TXC DPLL > device and TX ref clock pin framework for E825 > The first one is false positive in my opinion. > > Did you mean those from patch 3/8? > It should be rather simple ones. Shall I submit it as a part of this series? > Or a new patch/patchset? (against next or net?)
Ugh, I think I missed that the caller looks at the ICE_FLAG_DPLL flag. So most of the deinit bugs are not actually bugs. You can add the fixes to this series.
