On Fri, Jun 05, 2026 at 02:06:26PM +0200, Przemyslaw Korba wrote:
> The low-latency (LL) PHY timer interface relies on a tight, atomic poll
> of the PF_SB_ATQBAL register with a 2ms timeout. After an NVM update /
> EMPR, FW may need significantly longer than 2ms to start responding to
> ATQBAL commands. The first PHY adjust or incval write issued by
> ice_ptp_rebuild_owner() fails with -ETIMEDOUT.
>
> Fix this by falling back to the existing SBQ-based PHY register write
> path when LL times out. This makes sure PTP is initialized when FW takes
> longer than expected to come back online.
>
> Steps to reproduce:
> ./nvmupdate64e -if devlink -f
> Update E810 card with nvmupdate64e, and observe dmesg errors:
> Failed to write PHC increment value, status -110
> PTP reset failed, error: -110 (-ETIMEDOUT)
>
> Fixes: ef9a64c07294 ("ice: implement low latency PHY timer updates")
> Signed-off-by: Przemyslaw Korba <[email protected]>
> ---
> v3:
> * actually add TIMEDOUT check in ice_prep_phy_adj_e810 (did do it)
> v2:
> * add TIMEDOUT check in ice_prep_phy_adj_e810 (did not do it)
> https://lore.kernel.org/intel-wired-lan/[email protected]/
> v1:
> https://lore.kernel.org/intel-wired-lan/[email protected]/
> ---
> drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 38 +++++++++++----------
> 1 file changed, 20 insertions(+), 18 deletions(-)
Reviewed-by: Simon Horman <[email protected]>
