> -----Original Message----- > From: Jacob Keller <[email protected]> > Sent: Friday, September 25, 2026 4:57 PM > To: Intel Wired LAN <[email protected]>; Machnikowski, Maciej > <[email protected]>; Keller, Jacob E <[email protected]>; > Korba, Przemyslaw <[email protected]>; Nguyen, Anthony L > <[email protected]>; Nitka, Grzegorz <[email protected]>; > Kubalewski, Arkadiusz <[email protected]> > Cc: Keller, Jacob E <[email protected]>; Machnikowski, Maciej > <[email protected]> > Subject: [PATCH iwl-net v3 09/15] ice: E825: clear PHY_REG_TX_MEMORY_STATUS > prior to soft reset > > The current implementation of ice_ptp_reset_ts_memory_eth56g() is flawed. > It tries to clear the timestamp memory by writing to the > PHY_REG_TX_MEMORY_STATUS region. This does not work properly, as it does not > trigger appropriate PHY actions. > > To clear outstanding timestamp memory, the driver must read the timestamps. > However, naively doing this as part of ice_ptp_reset_ts_memory() is > problematic. When reading the timestamp index, hardware kicks off a chain of > actions including clearing the ready bitmap index, and decrementing an > internal counter if the timestamp index was marked as valid. > > This can potentially leave the internal hardware counter out of sync with the > actual number of timestamps. This occurs because the PHY_REG_TX_MEMORY_STATUS > region is not zero-initialized when the device boots up. Instead, it is > filled with garbage. On a cold power on, attempts to read the stale data > result in the hardware triggering a counter decrement for a timestamp that > never happened. This underflows the counter, and prevents new timestamp > interrupts from being triggered for real timestamp requests. > > We must read the PHY_REG_TX_MEMORY_STATUS in order to clear stale timestamps. > But doing so may cause a desync with the counter. To prevent issues, perform > this clearing always and only right before initiating a PHY soft reset. > > The soft reset will clear and reset the internal counter and the ready > bitmap. The reads to PHY_REG_TX_MEMORY_STATUS will reset the region valid > bits ensuring that no stale data is left behind. This combination ensures > that we always have a clean slate with no stale data and with the counter > properly reset to zero. > > If a read fails (i.e. due to a transient sideband queue failure) it is not > treated as a fatal error. There is already a dynamic debug message for each > read failure. Keep track of the total number of timestamp registers that fail > for a given port and log a warning message indicating the total number of > failures. Continuing is acceptable as clearing the memory is a precaution > against faulty software. Correct software access won't read the index twice > and won't read it at all except when it has already confirmed that the index > is valid by reading ice_get_phy_tx_tstamp_ready(). > > Fixes: 3ec46e157c7f ("ice: perform PHY soft reset for E825C ports at > initialization") > Reviewed-by: Maciek Machnikowski <[email protected]> > Signed-off-by: Jacob Keller <[email protected]> > --- > drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 100 > +++++++++++++++------------- > 1 file changed, 52 insertions(+), 48 deletions(-)
Tested-by: Alexander Nowlin <[email protected]>
