Dear Folk, Please share good resource for below mention position;
*Please share resume at **gudhal.chau...@techwiresol.com* *Role : ASIC Design/Verification Engineer* [NOTE: Need hands-on folks, not interested in managers] *Status:* Urgent *Industries:* IDM/Fabless Semi; Consumer Electronics and Networking *Levels:* Intermediate / Senior *Type:* Contract ~ 6 to 12 mths, extendable *No of positions:* 8+ *Deployment location options:* Silicon Valley, CA; Sacramento, CA; Phoenix, AZ *Key qualifying skills:* • Around 4 to 7 years of demonstrable industrial experience ASIC/SoC verification experience. FPGA verification also OK • Must be very well-versed with hands-on Verilog coding, testbenches. • Experience with SystemVerilog verification (OVM or UVM) methodology • Scripting languages, e.g. – Perl, Tcl, Python or Shell scripting Desirables (any) • C++ programming experience • SystemC Experience. *Regards* *Gudhal Chauhan* *Techwire Solutions, Inc* 101 Hudson St, Suite # 2100, Jersey City, NJ 07302 USA Phone: 201-884-6357 [O] Email: gudhal.chau...@techwiresol.com || Web: www.techwiresol.com *Office Locations: New Jersey || California || Washington || New Delhi || Noida || Pune || Hyderabad * -- You received this message because you are subscribed to the Google Groups "International SAP Projects" group. To unsubscribe from this group and stop receiving emails from it, send an email to international-sap-projects+unsubscr...@googlegroups.com. To post to this group, send email to international-sap-projects@googlegroups.com. Visit this group at http://groups.google.com/group/international-sap-projects. For more options, visit https://groups.google.com/groups/opt_out.
