Signed-off-by: David Woodhouse <david.woodho...@intel.com>
---
 drivers/iommu/intel-svm.c   | 115 +++++++++++++++++++++++++++++++++++++++++++-
 include/linux/intel-iommu.h |  21 ++++++++
 2 files changed, 134 insertions(+), 2 deletions(-)

diff --git a/drivers/iommu/intel-svm.c b/drivers/iommu/intel-svm.c
index 1260e87..ace1e32 100644
--- a/drivers/iommu/intel-svm.c
+++ b/drivers/iommu/intel-svm.c
@@ -356,10 +356,121 @@ int intel_svm_unbind_mm(struct device *dev, int pasid)
 }
 EXPORT_SYMBOL_GPL(intel_svm_unbind_mm);
 
+/* Page request queue descriptor */
+struct page_req_dsc {
+       u64 srr:1;
+       u64 bof:1;
+       u64 pasid_present:1;
+       u64 lpig:1;
+       u64 pasid:20;
+       u64 bus:8;
+       u64 private:23;
+       u64 prg_index:9;
+       u64 rd_req:1;
+       u64 wr_req:1;
+       u64 exe_req:1;
+       u64 priv_req:1;
+       u64 devfn:8;
+       u64 addr:52;
+};
 
+#define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x10)
 static irqreturn_t prq_event_thread(int irq, void *d)
 {
        struct intel_iommu *iommu = d;
-       printk("PRQ event on %s\n", iommu->name);
-       return IRQ_HANDLED;
+       struct intel_svm *svm = NULL;
+       int head, tail, handled = 0;
+
+       tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
+       head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
+       while (head != tail) {
+               struct vm_area_struct *vma;
+               struct page_req_dsc *req;
+               struct qi_desc resp;
+               int ret, result;
+               u64 address;
+
+               handled = 1;
+
+               req = &iommu->prq[head / sizeof(*req)];
+
+               result = QI_RESP_INVALID;
+               address = req->addr << PAGE_SHIFT;
+               if (!req->pasid_present) {
+                       pr_err("%s: Page request without PASID: %08llx 
%08llx\n",
+                              iommu->name, ((unsigned long long *)req)[0],
+                              ((unsigned long long *)req)[1]);
+                       goto inval_req;
+               }
+
+               if (!svm || svm->pasid != req->pasid) {
+                       mutex_lock(&pasid_mutex);
+                       if (svm)
+                               kref_put(&svm->kref, &intel_mm_free);
+
+                       svm = idr_find(&iommu->pasid_idr, req->pasid);
+                       if (!svm) {
+                               pr_err("%s: Page request for invalid PASID %d: 
%08llx %08llx\n",
+                                      iommu->name, req->pasid, ((unsigned long 
long *)req)[0],
+                                      ((unsigned long long *)req)[1]);
+                               mutex_unlock(&pasid_mutex);
+                               goto inval_req;
+                       }
+                       /* Strictly speaking, we shouldn't need this. It is 
forbidden
+                          to unbind the PASID while there may still be 
requests in
+                          flight. But let's do it anyway. */
+                       kref_get(&svm->kref);
+                       mutex_unlock(&pasid_mutex);
+               }
+
+               result = QI_RESP_FAILURE;
+               down_read(&svm->mm->mmap_sem);
+               vma = find_extend_vma(svm->mm, address);
+               if (!vma || address < vma->vm_start)
+                       goto hard_fault;
+
+               ret = handle_mm_fault(svm->mm, vma, address,
+                                     req->wr_req ? FAULT_FLAG_WRITE : 0);
+               if (ret & VM_FAULT_ERROR)
+                       goto hard_fault;
+
+               result = QI_RESP_SUCCESS;
+       hard_fault:
+               up_read(&svm->mm->mmap_sem);
+       inval_req:
+               /* Accounting for major/minor faults? */
+
+               if (req->lpig) {
+                       /* Page Group Response */
+                       resp.low = QI_PGRP_PASID(req->pasid) |
+                               QI_PGRP_DID((req->bus << 8) | req->devfn) |
+                               QI_PGRP_PASID_P(req->pasid_present) |
+                               QI_PGRP_RESP_TYPE;
+                       resp.high = QI_PGRP_IDX(req->prg_index) |
+                               QI_PGRP_PRIV(req->private) | 
QI_PGRP_RESP_CODE(result);
+
+                       qi_submit_sync(&resp, svm->iommu);
+               } else if (req->srr) {
+                       /* Page Stream Response */
+                       resp.low = QI_PSTRM_IDX(req->prg_index) |
+                               QI_PSTRM_PRIV(req->private) | 
QI_PSTRM_BUS(req->bus) |
+                               QI_PSTRM_PASID(req->pasid) | QI_PSTRM_RESP_TYPE;
+                       resp.high = QI_PSTRM_ADDR(address) | 
QI_PSTRM_DEVFN(req->devfn) |
+                               QI_PSTRM_RESP_CODE(result);
+
+                       qi_submit_sync(&resp, svm->iommu);
+               }
+
+               head = (head + sizeof(*req)) & PRQ_RING_MASK;
+       }
+
+       if (svm) {
+               mutex_lock(&pasid_mutex);
+               kref_put(&svm->kref, &intel_mm_free);
+               mutex_unlock(&pasid_mutex);
+       }
+
+       dmar_writeq(iommu->reg + DMAR_PQH_REG, tail);
+
+       return IRQ_RETVAL(handled);
 }
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
index bf034b0..aa7e02d 100644
--- a/include/linux/intel-iommu.h
+++ b/include/linux/intel-iommu.h
@@ -266,6 +266,8 @@ enum {
 #define QI_EIOTLB_TYPE         0x6
 #define QI_PC_TYPE             0x7
 #define QI_DEIOTLB_TYPE                0x8
+#define QI_PGRP_RESP_TYPE      0x9
+#define QI_PSTRM_RESP_TYPE     0xa
 
 #define QI_IEC_SELECTIVE       (((u64)1) << 4)
 #define QI_IEC_IIDEX(idx)      (((u64)(idx & 0xffff) << 32))
@@ -316,6 +318,25 @@ enum {
 #define QI_DEV_EIOTLB_QDEP(qd) (((qd) & 0x1f) << 16)
 #define QI_DEV_EIOTLB_MAX_INVS 32
 
+#define QI_PGRP_IDX(idx)       (((u64)(idx)) << 55)
+#define QI_PGRP_PRIV(priv)     (((u64)(priv)) << 32)
+#define QI_PGRP_RESP_CODE(res) ((u64)(res))
+#define QI_PGRP_PASID(pasid)   (((u64)(pasid)) << 32)
+#define QI_PGRP_DID(did)       (((u64)(did)) << 16)
+#define QI_PGRP_PASID_P(p)     (((u64)(p)) << 4)
+
+#define QI_PSTRM_ADDR(addr)    (((u64)(addr)) & VTD_PAGE_MASK)
+#define QI_PSTRM_DEVFN(devfn)  (((u64)(devfn)) << 4)
+#define QI_PSTRM_RESP_CODE(res)        ((u64)(res))
+#define QI_PSTRM_IDX(idx)      (((u64)(idx)) << 55)
+#define QI_PSTRM_PRIV(priv)    (((u64)(priv)) << 32)
+#define QI_PSTRM_BUS(bus)      (((u64)(bus)) << 24)
+#define QI_PSTRM_PASID(pasid)  (((u64)(pasid)) << 4)
+
+#define QI_RESP_SUCCESS                0x0
+#define QI_RESP_INVALID                0x1
+#define QI_RESP_FAILURE                0xf
+
 #define QI_GRAN_ALL_ALL                        0
 #define QI_GRAN_NONG_ALL               1
 #define QI_GRAN_NONG_PASID             2
-- 
2.4.3

-- 
David Woodhouse                            Open Source Technology Centre
david.woodho...@intel.com                              Intel Corporation

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