On Mon, Jan 16, 2017 at 01:23:36AM -0600, Suravee Suthikulpanit wrote:
> + pi = container_of(event->pmu, struct perf_amd_iommu, pmu);
> + hwc->idx = pi->idx;
> + hwc->config = event->attr.config;
> + hwc->extra_reg.config = event->attr.config1;
> static void perf_iommu_enable_event(struct perf_event *ev)
> {
> + struct hw_perf_event *hwc = &ev->hw;
> u8 csource = _GET_CSOURCE(ev);
> u16 devid = _GET_DEVID(ev);
> u8 bank = _GET_BANK(ev);
> @@ -253,30 +248,34 @@ static void perf_iommu_enable_event(struct perf_event
> *ev)
> u64 reg = 0ULL;
>
> reg = csource;
> - amd_iommu_pc_set_reg(0, bank, cntr,
> + amd_iommu_pc_set_reg(hwc->idx, bank, cntr,
> IOMMU_PC_COUNTER_SRC_REG, ®);
Please explain about this IOMMU crud, this looks like fail.
hwc->idx should be the counter, not a random pmu index.
But instead it looks like you get the counter form:
#define _GET_CNTR(ev) ((u8)(ev->hw.extra_reg.reg))
Which is absolutely insane.
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