On Wed, 14 Jun 2017 15:23:00 -0700
Jacob Pan <jacob.jun....@linux.intel.com> wrote:

> When PASID table pointer of an assigned device is bond to a guest,

s/bond/bound/

> the first level page tables are managed by the guest. However, only
> host/physical IOMMU can detect fault events, e.g. page requests.
> Therefore, we need to keep track of which device has its PASID table
> pointer bond to a guest such that page request and other events can

same and throughout...

> be propagated to the guest as needed.
> 
> Signed-off-by: Jacob Pan <jacob.jun....@linux.intel.com>
> Signed-off-by: Ashok Raj <ashok....@intel.com>
> ---
>  drivers/iommu/intel-iommu.c | 19 +------------------
>  include/linux/intel-iommu.h | 19 +++++++++++++++++++
>  2 files changed, 20 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
> index 6b8e997..9765277 100644
> --- a/drivers/iommu/intel-iommu.c
> +++ b/drivers/iommu/intel-iommu.c
> @@ -416,24 +416,6 @@ struct dmar_domain {
>                                          iommu core */
>  };
>  
> -/* PCI domain-device relationship */
> -struct device_domain_info {
> -     struct list_head link;  /* link to domain siblings */
> -     struct list_head global; /* link to global list */
> -     u8 bus;                 /* PCI bus number */
> -     u8 devfn;               /* PCI devfn number */
> -     u8 pasid_supported:3;
> -     u8 pasid_enabled:1;
> -     u8 pri_supported:1;
> -     u8 pri_enabled:1;
> -     u8 ats_supported:1;
> -     u8 ats_enabled:1;
> -     u8 ats_qdep;
> -     struct device *dev; /* it's NULL for PCIe-to-PCI bridge */
> -     struct intel_iommu *iommu; /* IOMMU used by this device */
> -     struct dmar_domain *domain; /* pointer to domain */
> -};
> -
>  struct dmar_rmrr_unit {
>       struct list_head list;          /* list of rmrr units   */
>       struct acpi_dmar_header *hdr;   /* ACPI header          */
> @@ -5547,6 +5529,7 @@ static int intel_iommu_bind_pasid_table(struct 
> iommu_domain *domain,
>                               DMA_CCMD_MASK_NOBIT,
>                               DMA_CCMD_DEVICE_INVL);
>       iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH);
> +     info->pasid_tbl_bond = 1;
>       spin_unlock_irqrestore(&iommu->lock, flags);
>  
>  
> diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
> index 8df6c91..ed39c56 100644
> --- a/include/linux/intel-iommu.h
> +++ b/include/linux/intel-iommu.h
> @@ -434,6 +434,25 @@ struct intel_iommu {
>       u32             flags;      /* Software defined flags */
>  };
>  
> +/* PCI domain-device relationship */
> +struct device_domain_info {
> +     struct list_head link;  /* link to domain siblings */
> +     struct list_head global; /* link to global list */
> +     u8 bus;                 /* PCI bus number */
> +     u8 devfn;               /* PCI devfn number */
> +     u8 pasid_supported:3;
> +     u8 pasid_enabled:1;
> +     u8 pasid_tbl_bond:1;    /* bond to guest PASID table */
> +     u8 pri_supported:1;
> +     u8 pri_enabled:1;
> +     u8 ats_supported:1;
> +     u8 ats_enabled:1;
> +     u8 ats_qdep;
> +     struct device *dev; /* it's NULL for PCIe-to-PCI bridge */
> +     struct intel_iommu *iommu; /* IOMMU used by this device */
> +     struct dmar_domain *domain; /* pointer to domain */
> +};
> +
>  static inline void __iommu_flush_cache(
>       struct intel_iommu *iommu, void *addr, int size)
>  {

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