Hi Will/Lorenzo/Marc, Any feedback on this series, please? Really appreciate if you can take a look and let us know.
Thanks, Shameer > -----Original Message----- > From: Shameerali Kolothum Thodi > Sent: Wednesday, September 27, 2017 2:33 PM > To: lorenzo.pieral...@arm.com; marc.zyng...@arm.com; > sudeep.ho...@arm.com; will.dea...@arm.com; robin.mur...@arm.com; > j...@8bytes.org; mark.rutl...@arm.com; r...@kernel.org > Cc: Gabriele Paoloni <gabriele.paol...@huawei.com>; John Garry > <john.ga...@huawei.com>; iommu@lists.linux-foundation.org; linux-arm- > ker...@lists.infradead.org; linux-a...@vger.kernel.org; > devicet...@vger.kernel.org; de...@acpica.org; Linuxarm > <linux...@huawei.com>; Wangzhou (B) <wangzh...@hisilicon.com>; > Guohanjun (Hanjun Guo) <guohan...@huawei.com>; Shameerali Kolothum > Thodi <shameerali.kolothum.th...@huawei.com> > Subject: [PATCH v8 0/5] iommu/smmu-v3: Workaround for hisilicon > 161010801 erratum(reserve HW MSI) > > On certain HiSilicon platforms (hip06/hip07) the GIC ITS and PCIe RC > deviates from the standard implementation and this breaks PCIe MSI > functionality when SMMU is enabled. > > The HiSilicon erratum 161010801 describes this limitation of certain > HiSilicon platforms to support the SMMU mappings for MSI transactions. > On these platforms GICv3 ITS translator is presented with the deviceID > by extending the MSI payload data to 64 bits to include the deviceID. > Hence, the PCIe controller on this platforms has to differentiate the MSI > payload against other DMA payload and has to modify the MSI payload. > This basically makes it difficult for this platforms to have a SMMU > translation for MSI. > > This patch implements an ACPI and DT based quirk to reserve the hw msi > regions in the smmu-v3 driver which means these address regions will > not be translated and will be excluded from iova allocations. > > To implement this quirk, the following changes are incorporated: > 1. Added a generic helper function to IORT code to retrieve the > associated ITS base address from a device IORT node. > 2. Added a generic helper function to of iommu code to retrieve the > associated msi controller base address from for a PCI RC > msi-mapping and also platform device msi-parent. > 3. Added quirk to SMMUv3 to retrieve the HW ITS address and replace > the default SW MSI reserve address based on the IORT SMMU model > or DT bindings. > > Changelog: > > v7 --> v8 > Addressed comments from Rob and Lorenzo: > -Modified to use DT compatible string for errata. > -Changed logic to retrieve the msi-parent for DT case. > > v6 --> v7 > Addressed request from Will to add DT support for the erratum: > - added bt binding > - add of_iommu_msi_get_resv_regions() > New arm64 silicon errata entry > Rename iort_iommu_{its->msi}_get_resv_regions > > v5 --> v6 > Addressed comments from Robin and Lorenzo: > -No change to patch#1 . > -Reverted v5 patch#2 as this might break the platforms where this quirk > is not applicable. Provided a generic function in iommu code and added > back the quirk implementation in SMMU v3 driver(patch#3) > > v4 --> v5 > Addressed comments from Robin and Lorenzo: > -Added a comment to make it clear that, for now, only straightforward > HW topologies are handled while reserving ITS regions(patch #1). > > v3 --> v4 > Rebased on 4.13-rc1. > Addressed comments from Robin, Will and Lorenzo: > -As suggested by Robin, moved the ITS msi reservation into > iommu_dma_get_resv_regions(). > -Added its_count != resv region failure case(patch #1). > > v2 --> v3 > Addressed comments from Lorenzo and Robin: > -Removed dev_is_pci() check in smmuV3 driver. > -Don't treat device not having an ITS mapping as an error in > iort helper function. > > v1 --> v2 > -patch 2/2: Invoke iort helper fn based on fwnode type(acpi). > > RFCv2 -->PATCH > -Incorporated Lorenzo's review comments. > > RFC v1 --> RFC v2 > Based on Robin's review comments, > -Removed the generic erratum framework. > -Using IORT/MADT tables to retrieve the ITS base addr instead of vendor > specific CSRT table. > > John Garry (2): > Doc: iommu/arm-smmu-v3: Add workaround for HiSilicon erratum > 161010801 > iommu/of: Add msi address regions reservation helper > > Shameer Kolothum (3): > ACPI/IORT: Add msi address regions reservation helper > iommu/dma: Add a helper function to reserve HW MSI address regions for > IOMMU drivers > iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801 > > Documentation/arm64/silicon-errata.txt | 1 + > .../devicetree/bindings/iommu/arm,smmu-v3.txt | 9 +- > drivers/acpi/arm64/iort.c | 96 > +++++++++++++++++++++- > drivers/iommu/arm-smmu-v3.c | 41 +++++++-- > drivers/iommu/dma-iommu.c | 19 +++++ > drivers/iommu/of_iommu.c | 95 +++++++++++++++++++++ > drivers/irqchip/irq-gic-v3-its.c | 3 +- > include/linux/acpi_iort.h | 7 +- > include/linux/dma-iommu.h | 7 ++ > include/linux/of_iommu.h | 10 +++ > 10 files changed, 276 insertions(+), 12 deletions(-) > > -- > 1.9.1 > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu