Hi Vivek, On 2018/3/28 12:37, Vivek Gautam wrote: > Hi Yisheng > > > On 3/28/2018 6:54 AM, Yisheng Xie wrote: >> Hi Vivek, >> >> On 2018/3/13 16:55, Vivek Gautam wrote: >>> +- power-domains: Specifiers for power domains required to be powered on >>> for >>> + the SMMU to operate, as per generic power domain >>> bindings. >>> + >> In this patchset, power-domains is not used right? And you just do the clock >> gating, >> but not power gating, right? > > We are handling the power-domains too. Please see the example in this binding > doc.
I see, but I do not find the point in code of these patchset, do you mean PMIC(e.g mmcc) will gate the power domain of SMMU(e.g. MDSS_GDSC of mmcc) when PMIC suspend? > >> >> Another question is if smmu do power gating, it will reset some of its >> registers, so >> it need save at suspend and restore at resume, right? > > Qualcomm implementation of the arm-smmu has the retenetion enabled. So the > smmu doesn't > loose state when power is pulled out of it. > And now we are just selectively enabling the runtime pm. So only the > platforms that can really > support runtime pm can enable it. Get it, thanks for your explain. Thanks Yisheng > > Thanks > Vivek >> >> Thanks >> Yisheng >> > > > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
