On Tue, 12 Jun 2018, Ricardo Neri wrote: > @@ -183,6 +184,8 @@ static irqreturn_t hardlockup_detector_irq_handler(int > irq, void *data) > if (!(hdata->flags & HPET_DEV_PERI_CAP)) > kick_timer(hdata); > > + pr_err("This interrupt should not have happened. Ensure delivery mode > is NMI.\n");
Eeew. > /** > + * hardlockup_detector_nmi_handler() - NMI Interrupt handler > + * @val: Attribute associated with the NMI. Not used. > + * @regs: Register values as seen when the NMI was asserted > + * > + * When an NMI is issued, look for hardlockups. If the timer is not periodic, > + * kick it. The interrupt is always handled when if delivered via the > + * Front-Side Bus. > + * > + * Returns: > + * > + * NMI_DONE if the HPET timer did not cause the interrupt. NMI_HANDLED > + * otherwise. > + */ > +static int hardlockup_detector_nmi_handler(unsigned int val, > + struct pt_regs *regs) > +{ > + struct hpet_hld_data *hdata = hld_data; > + unsigned int use_fsb; > + > + /* > + * If FSB delivery mode is used, the timer interrupt is programmed as > + * edge-triggered and there is no need to check the ISR register. > + */ > + use_fsb = hdata->flags & HPET_DEV_FSB_CAP; > + > + if (!use_fsb && !is_hpet_wdt_interrupt(hdata)) > + return NMI_DONE; So for 'use_fsb == True' every single NMI will fall through into the watchdog code below. > + inspect_for_hardlockups(regs); > + > + if (!(hdata->flags & HPET_DEV_PERI_CAP)) > + kick_timer(hdata); And in case that the HPET does not support periodic mode this reprogramms the timer on every NMI which means that while perf is running the watchdog will never ever detect anything. Aside of that, reading TWO HPET registers for every NMI is insane. HPET access is horribly slow, so any high frequency perf monitoring will take a massive performance hit. Thanks, tglx _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu