On Thu, Jul 18, 2019 at 11:52 AM Christoph Hellwig <h...@lst.de> wrote: > > On Thu, Jul 18, 2019 at 10:49:34AM +0200, Christoph Hellwig wrote: > > On Thu, Jul 18, 2019 at 01:45:16PM +1000, Oliver O'Halloran wrote: > > > > Other than m68k, mips, and arm64, everybody else that doesn't have > > > > ARCH_NO_COHERENT_DMA_MMAP set uses this default implementation, so > > > > I assume this behavior is acceptable on those architectures. > > > > > > It might be acceptable, but there's no reason to use pgport_noncached > > > if the platform supports cache-coherent DMA. > > > > > > Christoph (+cc) made the change so maybe he saw something we're missing. > > > > I always found the forcing of noncached access even for coherent > > devices a little odd, but this was inherited from the previous > > implementation, which surprised me a bit as the different attributes > > are usually problematic even on x86. Let me dig into the history a > > bit more, but I suspect the righ fix is to default to cached mappings > > for coherent devices. > > Ok, some history: > > The generic dma mmap implementation, which we are effectively still > using today was added by: > > commit 64ccc9c033c6089b2d426dad3c56477ab066c999 > Author: Marek Szyprowski <m.szyprow...@samsung.com> > Date: Thu Jun 14 13:03:04 2012 +0200 > > common: dma-mapping: add support for generic dma_mmap_* calls > > and unconditionally uses pgprot_noncached in dma_common_mmap, which is > then used as the fallback by dma_mmap_attrs if no ->mmap method is > present. At that point we already had the powerpc implementation > that only uses pgprot_noncached for non-coherent mappings, and > the arm one, which uses pgprot_writecombine if DMA_ATTR_WRITE_COMBINE > is set and otherwise pgprot_dmacoherent, which seems to be uncached. > Arm did support coherent platforms at that time, but they might have > been an afterthought and not handled properly.
Cache-coherent devices are still very rare on 32-bit ARM. Among the callers of dma_mmap_coherent(), almost all are in platform specific device drivers that only ever run on noncoherent ARM SoCs, which explains why nobody would have noticed problems. There is also a difference in behavior between ARM and PowerPC when dealing with mismatched cacheability attributes: If the same page is mapped as both cached and uncached to, this may cause silent undefined behavior on ARM, while PowerPC should enter a checkstop as soon as it notices. Arnd _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu