On Fri, 2019-10-11 at 17:29 +0100, Will Deacon wrote: > On Wed, Oct 09, 2019 at 09:19:02PM +0800, Yong Wu wrote: > > Use writel for the register F_MMU_INV_RANGE which is for triggering the > > HW work. We expect all the setting(iova_start/iova_end...) have already > > been finished before F_MMU_INV_RANGE. > > > > Signed-off-by: Anan.Sun <anan....@mediatek.com> > > Signed-off-by: Yong Wu <yong...@mediatek.com> > > --- > > This is a improvement rather than fixing a issue. > > --- > > drivers/iommu/mtk_iommu.c | 3 +-- > > 1 file changed, 1 insertion(+), 2 deletions(-) > > > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > > index 24a13a6..607f92c 100644 > > --- a/drivers/iommu/mtk_iommu.c > > +++ b/drivers/iommu/mtk_iommu.c > > @@ -187,8 +187,7 @@ static void mtk_iommu_tlb_add_flush(unsigned long iova, > > size_t size, > > writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A); > > writel_relaxed(iova + size - 1, > > data->base + REG_MMU_INVLD_END_A); > > - writel_relaxed(F_MMU_INV_RANGE, > > - data->base + REG_MMU_INVALIDATE); > > + writel(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE); > > I don't understand this change. > > Why is it an "improvement" and which accesses are you ordering with the > writel?
The register(F_MMU_INV_RANGE) will trigger HW to begin flush range. HW expect the other register iova_start/end/flush_type always is ready before trigger. thus I'd like use writel to guarantee the previous register has been finished. I didn't see the writel_relaxed cause some error in practice, we only think writel is necessary here in theory. so call it "improvement". > > Will