On Mon, 2019-10-14 at 15:04 +0100, Robin Murphy wrote: > On 14/10/2019 07:38, Yong Wu wrote: > > Use writel for the register F_MMU_INV_RANGE which is for triggering the > > HW work. We expect all the setting(iova_start/iova_end...) have already > > been finished before F_MMU_INV_RANGE. > > For Arm CPUs, these registers should be mapped as Device memory, > therefore the same-peripheral rule should implicitly enforce that the > accesses are made in program order, hence you're unlikely to have seen a > problem in reality. However, the logical reasoning for the change seems > valid in general, so I'd argue that it's still worth making if only for > the sake of good practice: > > Acked-by: Robin Murphy <robin.mur...@arm.com>
Thanks very much for the view. If this patch is not so necessary, I will remove it this time. > > > Signed-off-by: Anan.Sun <anan....@mediatek.com> > > Signed-off-by: Yong Wu <yong...@mediatek.com> > > --- > > drivers/iommu/mtk_iommu.c | 3 +-- > > 1 file changed, 1 insertion(+), 2 deletions(-) > > > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > > index dbbacc3..d285457 100644 > > --- a/drivers/iommu/mtk_iommu.c > > +++ b/drivers/iommu/mtk_iommu.c > > @@ -187,8 +187,7 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned > > long iova, size_t size, > > writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A); > > writel_relaxed(iova + size - 1, > > data->base + REG_MMU_INVLD_END_A); > > - writel_relaxed(F_MMU_INV_RANGE, > > - data->base + REG_MMU_INVALIDATE); > > + writel(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE); > > > > /* tlb sync */ > > ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, > > > > _______________________________________________ > Linux-mediatek mailing list > linux-media...@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek