On Wed, Dec 04, 2019 at 04:44:59PM +0000, Robin Murphy wrote: > On 22/11/2019 11:31 pm, Jordan Crouse wrote: > >Add implementation specific support to enable split pagetables for > >SMMU implementations attached to Adreno GPUs on Qualcomm targets. > > > >To enable split pagetables the driver will set an attribute on the domain. > >if conditions are correct, set up the hardware to support equally sized > >TTBR0 and TTBR1 regions and programs the domain pagetable to TTBR1 to make > >it available for global buffers while allowing the GPU the chance to > >switch the TTBR0 at runtime for per-context pagetables. > > > >After programming the context, the value of the domain attribute can be > >queried to see if split pagetables were successfully programmed. The > >domain geometry will be updated so that the caller can determine the > >start of the region to generate correct virtual addresses. > > Why is any of this in impl? It all looks like perfectly generic > architectural TTBR1 setup to me. As long as DOMAIN_ATTR_SPLIT_TABLES is > explicitly an opt-in for callers, I'm OK with them having to trust that > SEP_UPSTREAM is good enough. Or, even better, make the value of > DOMAIN_ATTR_SPLIT_TABLES not a boolean but the actual split point, where the > default of 0 would logically mean "no split".
(apologies if you get multiple copies of this email, I have tickets in with the CAF IT folks). I made it impl specific because my impression from the previous conversations was that setting up the T0 space but leaving TTBR0 un-programmed was a silly thing that was unique to the Adreno GPU. I don't mind moving it to the generic code since that saves us from some silly compatible string games. I like the idea of DOMAIN_ATTR_SPLIT_TABLES returning the split point but would we want to allow the user to try to specific a desired split point ahead of time? It is my impression that we only have a handful of valid SEP values and I'm not sure what the right response would be if the user specified an incorrect one. So far I've not found a use for anything except SEP_UPSTREAM but I have the extreme luxury of a SMMU with an actual 49 bit IAS. New patchset coming soon. Thanks, Jordan -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
