[PATCH v2 19/19] iommu/mediatek: Add multiple mtk_iommu_domain support for mt6779

[Chao Hao]

For mt6779, it need to support three mtk_iommu_domains, every
mtk_iommu_domain's iova space is different.
Three mtk_iommu_domains is as below:
1. Normal mtk_iommu_domain exclude 0x4000_0000~0x47ff_ffff and
   0x7da0_0000~7fbf_ffff.
2. CCU mtk_iommu_domain include 0x4000_0000~0x47ff_ffff.
3. VPU mtk_iommu_domain 0x7da0_0000~0x7fbf_ffff.

Signed-off-by: Chao Hao <chao....@mediatek.com>
---
 drivers/iommu/mtk_iommu.c | 45 +++++++++++++++++++++++++++++++++++++--
 1 file changed, 43 insertions(+), 2 deletions(-)

diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index ab09f435d437..d56254883541 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -134,6 +134,30 @@ const struct mtk_domain_data single_dom = {
        .max_iova = DMA_BIT_MASK(32)
 };
 
+/*
+ * related file: mt6779-larb-port.h
+ */
+const struct mtk_domain_data mt6779_multi_dom[] = {
+       /* normal domain */
+       {
+        .min_iova = 0x0,
+        .max_iova = DMA_BIT_MASK(32),
+       },
+       /* ccu domain */
+       {
+        .min_iova = 0x40000000,
+        .max_iova = 0x48000000 - 1,
+        .port_mask = {MTK_M4U_ID(9, 21), MTK_M4U_ID(9, 22),
+                      MTK_M4U_ID(12, 0), MTK_M4U_ID(12, 1)}
+       },
+       /* vpu domain */
+       {
+        .min_iova = 0x7da00000,
+        .max_iova = 0x7fc00000 - 1,
+        .port_mask = {MTK_M4U_ID(13, 0)}
+       }
+};
+
 static struct mtk_iommu_pgtable *share_pgtable;
 static const struct iommu_ops mtk_iommu_ops;
 
@@ -1050,6 +1074,21 @@ static const struct dev_pm_ops mtk_iommu_pm_ops = {
        SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume)
 };
 
+static const struct mtk_iommu_resv_iova_region mt6779_iommu_rsv_list[] = {
+       {
+               .dom_id = 0,
+               .iova_base = 0x40000000,        /* CCU */
+               .iova_size = 0x8000000,
+               .type = IOMMU_RESV_RESERVED,
+       },
+       {
+               .dom_id = 0,
+               .iova_base = 0x7da00000,        /* VPU/MDLA */
+               .iova_size = 0x2700000,
+               .type = IOMMU_RESV_RESERVED,
+       },
+};
+
 static const struct mtk_iommu_plat_data mt2712_data = {
        .m4u_plat     = M4U_MT2712,
        .has_4gb_mode = true,
@@ -1063,8 +1102,10 @@ static const struct mtk_iommu_plat_data mt2712_data = {
 
 static const struct mtk_iommu_plat_data mt6779_data = {
        .m4u_plat = M4U_MT6779,
-       .dom_cnt = 1,
-       .dom_data = &single_dom,
+       .resv_cnt     = ARRAY_SIZE(mt6779_iommu_rsv_list),
+       .resv_region  = mt6779_iommu_rsv_list,
+       .dom_cnt = ARRAY_SIZE(mt6779_multi_dom),
+       .dom_data = mt6779_multi_dom,
        .larbid_remap[0] = {0, 1, 2, 3, 5, 7, 10, 9},
        /* vp6a, vp6b, mdla/core2, mdla/edmc*/
        .larbid_remap[1] = {2, 0, 3, 1},
-- 
2.18.0
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