On Sun, Jun 28, 2020 at 07:28:38PM -0700, Krishna Reddy wrote:
> Add global/context fault hooks to allow NVIDIA SMMU implementation
> handle faults across multiple SMMUs.
>
> Signed-off-by: Krishna Reddy <vdu...@nvidia.com>
> +static irqreturn_t nvidia_smmu_global_fault_inst(int irq,
> + struct arm_smmu_device *smmu,
> + int inst)
> +{
> + u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
> + void __iomem *gr0_base = nvidia_smmu_page(smmu, inst, 0);
> +
> + gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
> + gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
> + gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
> + gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
> +
> + if (!gfsr)
> + return IRQ_NONE;
Could move this before gfsynr readings to save some readl() for
!gfsr cases?
> +static irqreturn_t nvidia_smmu_context_fault_bank(int irq,
> + void __iomem *cb_base = nvidia_smmu_page(smmu, inst, smmu->numpage +
> idx);
[...]
> + fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
[...]
> + writel_relaxed(fsr, cb_base + ARM_SMMU_CB_FSR);
It reads FSR of the default inst (1st), but clears the FSR of
corresponding inst -- just want to make sure that this is okay
and intended.
> @@ -185,7 +283,8 @@ struct arm_smmu_device *nvidia_smmu_impl_init(struct
> arm_smmu_device *smmu)
> }
>
> nvidia_smmu->smmu.impl = &nvidia_smmu_impl;
> - /* Free the arm_smmu_device struct allocated in arm-smmu.c.
> + /*
> + * Free the arm_smmu_device struct allocated in arm-smmu.c.
> * Once this function returns, arm-smmu.c would use arm_smmu_device
> * allocated as part of nvidia_smmu struct.
> */
Hmm, this coding style fix should be probably squashed into PATCH-1?
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