Hi, Thomas, Andy, et al, On Thu, Aug 27, 2020 at 08:06:34AM -0700, Fenghua Yu wrote: > A PASID is allocated for an "mm" the first time any thread binds > to an SVM capable device and is freed from the "mm" when the SVM is > unbound by the last thread. It's possible for the "mm" to have different > PASID values in different binding/unbinding SVM cycles. > > The mm's PASID (non-zero for valid PASID or 0 for invalid PASID) is > propagated to per-thread PASID MSR for all threads within the mm through > through IPI, context switch, or inherit to ensure a running thread has > the right PASID MSR matching the mm's PASID. > > Suggested-by: Andy Lutomirski <l...@kernel.org> > Signed-off-by: Fenghua Yu <fenghua...@intel.com> > Reviewed-by: Tony Luck <tony.l...@intel.com> > --- > v7: > - Don't fix up PASID in #GP. Instead, update the PASID MSR by IPI and > context switch after PASID allocation and free. Inherit PASID from > parent. (Andy) > > Before v7: > - Allocate a PASID for the mm and free it until mm exit.
This is a friendly reminder. Any comment on this series? This patch (9/9) is essentially the only changed patch that implements updating PASID MSR for a thread by IPI and context switch per Andy's comment. Thank you very much in advance! -Fenghua _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
