Add "cfg" as a parameter for some macros. This is a preparing patch for
mediatek extend the lvl1 pgtable. No functional change.

Signed-off-by: Yong Wu <yong...@mediatek.com>
---
 drivers/iommu/io-pgtable-arm-v7s.c | 34 +++++++++++++++---------------
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/drivers/iommu/io-pgtable-arm-v7s.c 
b/drivers/iommu/io-pgtable-arm-v7s.c
index a3b3e9147b8d..8362fdf76657 100644
--- a/drivers/iommu/io-pgtable-arm-v7s.c
+++ b/drivers/iommu/io-pgtable-arm-v7s.c
@@ -53,17 +53,17 @@
 #define ARM_V7S_LVL_SHIFT(lvl)         (ARM_V7S_ADDR_BITS - (4 + 8 * (lvl)))
 #define ARM_V7S_TABLE_SHIFT            10
 
-#define ARM_V7S_PTES_PER_LVL(lvl)      (1 << _ARM_V7S_LVL_BITS(lvl))
-#define ARM_V7S_TABLE_SIZE(lvl)                                                
\
-       (ARM_V7S_PTES_PER_LVL(lvl) * sizeof(arm_v7s_iopte))
+#define ARM_V7S_PTES_PER_LVL(lvl, cfg) (1 << _ARM_V7S_LVL_BITS(lvl))
+#define ARM_V7S_TABLE_SIZE(lvl, cfg)                                   \
+       (ARM_V7S_PTES_PER_LVL(lvl, cfg) * sizeof(arm_v7s_iopte))
 
 #define ARM_V7S_BLOCK_SIZE(lvl)                (1UL << ARM_V7S_LVL_SHIFT(lvl))
 #define ARM_V7S_LVL_MASK(lvl)          ((u32)(~0U << ARM_V7S_LVL_SHIFT(lvl)))
 #define ARM_V7S_TABLE_MASK             ((u32)(~0U << ARM_V7S_TABLE_SHIFT))
-#define _ARM_V7S_IDX_MASK(lvl)         (ARM_V7S_PTES_PER_LVL(lvl) - 1)
-#define ARM_V7S_LVL_IDX(addr, lvl)     ({                              \
+#define _ARM_V7S_IDX_MASK(lvl, cfg)    (ARM_V7S_PTES_PER_LVL(lvl, cfg) - 1)
+#define ARM_V7S_LVL_IDX(addr, lvl, cfg)        ({                      \
        int _l = lvl;                                                   \
-       ((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l); \
+       ((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l, cfg); \
 })
 
 /*
@@ -239,7 +239,7 @@ static void *__arm_v7s_alloc_table(int lvl, gfp_t gfp,
        struct device *dev = cfg->iommu_dev;
        phys_addr_t phys;
        dma_addr_t dma;
-       size_t size = ARM_V7S_TABLE_SIZE(lvl);
+       size_t size = ARM_V7S_TABLE_SIZE(lvl, cfg);
        void *table = NULL;
 
        if (lvl == 1)
@@ -285,7 +285,7 @@ static void __arm_v7s_free_table(void *table, int lvl,
 {
        struct io_pgtable_cfg *cfg = &data->iop.cfg;
        struct device *dev = cfg->iommu_dev;
-       size_t size = ARM_V7S_TABLE_SIZE(lvl);
+       size_t size = ARM_V7S_TABLE_SIZE(lvl, cfg);
 
        if (!cfg->coherent_walk)
                dma_unmap_single(dev, __arm_v7s_dma_addr(table), size,
@@ -429,7 +429,7 @@ static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data,
                        arm_v7s_iopte *tblp;
                        size_t sz = ARM_V7S_BLOCK_SIZE(lvl);
 
-                       tblp = ptep - ARM_V7S_LVL_IDX(iova, lvl);
+                       tblp = ptep - ARM_V7S_LVL_IDX(iova, lvl, cfg);
                        if (WARN_ON(__arm_v7s_unmap(data, NULL, iova + i * sz,
                                                    sz, lvl, tblp) != sz))
                                return -EINVAL;
@@ -482,7 +482,7 @@ static int __arm_v7s_map(struct arm_v7s_io_pgtable *data, 
unsigned long iova,
        int num_entries = size >> ARM_V7S_LVL_SHIFT(lvl);
 
        /* Find our entry at the current level */
-       ptep += ARM_V7S_LVL_IDX(iova, lvl);
+       ptep += ARM_V7S_LVL_IDX(iova, lvl, cfg);
 
        /* If we can install a leaf entry at this level, then do so */
        if (num_entries)
@@ -554,7 +554,7 @@ static void arm_v7s_free_pgtable(struct io_pgtable *iop)
        struct arm_v7s_io_pgtable *data = io_pgtable_to_data(iop);
        int i;
 
-       for (i = 0; i < ARM_V7S_PTES_PER_LVL(1); i++) {
+       for (i = 0; i < ARM_V7S_PTES_PER_LVL(1, &data->iop.cfg); i++) {
                arm_v7s_iopte pte = data->pgd[i];
 
                if (ARM_V7S_PTE_IS_TABLE(pte, 1))
@@ -606,9 +606,9 @@ static size_t arm_v7s_split_blk_unmap(struct 
arm_v7s_io_pgtable *data,
        if (!tablep)
                return 0; /* Bytes unmapped */
 
-       num_ptes = ARM_V7S_PTES_PER_LVL(2);
+       num_ptes = ARM_V7S_PTES_PER_LVL(2, cfg);
        num_entries = size >> ARM_V7S_LVL_SHIFT(2);
-       unmap_idx = ARM_V7S_LVL_IDX(iova, 2);
+       unmap_idx = ARM_V7S_LVL_IDX(iova, 2, cfg);
 
        pte = arm_v7s_prot_to_pte(arm_v7s_pte_to_prot(blk_pte, 1), 2, cfg);
        if (num_entries > 1)
@@ -650,7 +650,7 @@ static size_t __arm_v7s_unmap(struct arm_v7s_io_pgtable 
*data,
        if (WARN_ON(lvl > 2))
                return 0;
 
-       idx = ARM_V7S_LVL_IDX(iova, lvl);
+       idx = ARM_V7S_LVL_IDX(iova, lvl, &iop->cfg);
        ptep += idx;
        do {
                pte[i] = READ_ONCE(ptep[i]);
@@ -736,7 +736,7 @@ static phys_addr_t arm_v7s_iova_to_phys(struct 
io_pgtable_ops *ops,
        u32 mask;
 
        do {
-               ptep += ARM_V7S_LVL_IDX(iova, ++lvl);
+               ptep += ARM_V7S_LVL_IDX(iova, ++lvl, &data->iop.cfg);
                pte = READ_ONCE(*ptep);
                ptep = iopte_deref(pte, lvl, data);
        } while (ARM_V7S_PTE_IS_TABLE(pte, lvl));
@@ -779,8 +779,8 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct 
io_pgtable_cfg *cfg,
 
        spin_lock_init(&data->split_lock);
        data->l2_tables = kmem_cache_create("io-pgtable_armv7s_l2",
-                                           ARM_V7S_TABLE_SIZE(2),
-                                           ARM_V7S_TABLE_SIZE(2),
+                                           ARM_V7S_TABLE_SIZE(2, cfg),
+                                           ARM_V7S_TABLE_SIZE(2, cfg),
                                            ARM_V7S_TABLE_SLAB_FLAGS, NULL);
        if (!data->l2_tables)
                goto out_free_data;
-- 
2.18.0
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